中国物理B ›› 2012, Vol. 21 ›› Issue (4): 48501-048501.doi: 10.1088/1674-1056/21/4/048501

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李聪,庄奕琪,张丽,包军林   

  • 收稿日期:2011-09-28 修回日期:2011-12-19 出版日期:2012-02-29 发布日期:2012-02-29
  • 通讯作者: 李聪,cong.li@mail.xidian.edu.cn E-mail:cong.li@mail.xidian.edu.cn

Analytical model including the fringing-induced barrier lowering effect for a dual-material surrounding-gate MOSFET with a high-$\kappa$ gate dielectric

Li Cong(李聪), Zhuang Yi-Qi(庄奕琪), Zhang Li(张丽), and Bao Jun-Lin(包军林)   

  1. School of Microelectronics, Xidian University, Xi'an 710071, China
  • Received:2011-09-28 Revised:2011-12-19 Online:2012-02-29 Published:2012-02-29
  • Contact: Li Cong,cong.li@mail.xidian.edu.cn E-mail:cong.li@mail.xidian.edu.cn
  • Supported by:
    Project supported by the Fundamental Research Funds for the Central Universities (Grant No. K50511250001) and the National Natural Science Foundation of China (Grant No. 61076101).

Abstract: By solving Poisson's equation in both semiconductor and gate insulator regions in the cylindrical coordinates, an analytical model for a dual-material surrounding-gate (DMSG) metal-oxide semiconductor field-effect transistor (MOSFET) with a high-$\kappa$ gate dielectric has been developed. Using the derived model, the influences of fringing-induced barrier lowering (FIBL) on surface potential, subthreshold current, DIBL, and subthreshold swing are investigated. It is found that for the same equivalent oxide thickness, the gate insulator with high-$\kappa$ dielectric degrades the short-channel performance of the DMSG MOSFET. The accuracy of the analytical model is verified by the good agreement of its results with that obtained from the ISE three-dimensional numerical device simulator.

Key words: high-$\kappa$ gate dielectric, fringing-induced barrier lowering, analytical model

中图分类号:  (Semiconductor-device characterization, design, and modeling)

  • 85.30.De
73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator)) 02.60.Cb (Numerical simulation; solution of equations)