中国物理B ›› 2023, Vol. 32 ›› Issue (4): 48501-048501.doi: 10.1088/1674-1056/ac9607

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Dynamic electrostatic-discharge path investigation relied on different impact energies in metal-oxide-semiconductor circuits

Tian-Tian Xie(谢田田)1,†, Jun Wang(王俊)2,†, Fei-Bo Du(杜飞波)1, Yang Yu(郁扬)2, Yan-Fei Cai(蔡燕飞)2, Er-Yuan Feng(冯二媛)2, Fei Hou(侯飞)1, and Zhi-Wei Liu(刘志伟)1,‡   

  1. 1 State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;
    2 Design Service, Semiconductor Manufacturing International Corporation, Shanghai 200120, China
  • 收稿日期:2022-07-17 修回日期:2022-09-15 接受日期:2022-09-29 出版日期:2023-03-10 发布日期:2023-03-17
  • 通讯作者: Zhi-Wei Liu E-mail:ziv_liu@hotmail.com
  • 基金资助:
    Project supported by the National Natural Science Foundation of China (Grant No. 61974017).

Dynamic electrostatic-discharge path investigation relied on different impact energies in metal-oxide-semiconductor circuits

Tian-Tian Xie(谢田田)1,†, Jun Wang(王俊)2,†, Fei-Bo Du(杜飞波)1, Yang Yu(郁扬)2, Yan-Fei Cai(蔡燕飞)2, Er-Yuan Feng(冯二媛)2, Fei Hou(侯飞)1, and Zhi-Wei Liu(刘志伟)1,‡   

  1. 1 State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;
    2 Design Service, Semiconductor Manufacturing International Corporation, Shanghai 200120, China
  • Received:2022-07-17 Revised:2022-09-15 Accepted:2022-09-29 Online:2023-03-10 Published:2023-03-17
  • Contact: Zhi-Wei Liu E-mail:ziv_liu@hotmail.com
  • Supported by:
    Project supported by the National Natural Science Foundation of China (Grant No. 61974017).

摘要: Gate-grounded n-channel metal-oxide-semiconductor (GGNMOS) devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction, easy triggering, and low power dissipation. We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies. This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground, and thus should be urgently analyzed and resolved. Transmission-line-pulse, human-body-modal, and light-emission tests were performed to explore the root cause.

关键词: electrostatic discharge, trigger voltage, latch up, dV/dt effect

Abstract: Gate-grounded n-channel metal-oxide-semiconductor (GGNMOS) devices have been widely implemented as power clamps to protect semiconductor devices from electrostatic discharge stress owing to their simple construction, easy triggering, and low power dissipation. We present a novel I-V characterization of the GGNMOS used as the power clamp in complementary metal-oxide-semiconductor circuits as a result of switching the ESD paths under different impact energies. This special effect could cause an unexpected latch-up or pre-failure phenomenon in some applications with relatively large capacitances from power supply to power ground, and thus should be urgently analyzed and resolved. Transmission-line-pulse, human-body-modal, and light-emission tests were performed to explore the root cause.

Key words: electrostatic discharge, trigger voltage, latch up, dV/dt effect

中图分类号:  (Semiconductor-device characterization, design, and modeling)

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