中国物理B ›› 2021, Vol. 30 ›› Issue (7): 78502-078502.doi: 10.1088/1674-1056/abe2fb

• • 上一篇    下一篇

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN

Xi-Kun Feng(冯希昆), Xiao-Feng Gu(顾晓峰), Qin-Ling Ma(马琴玲), Yan-Ni Yang(杨燕妮), and Hai-Lian Liang(梁海莲)†   

  1. Engineering Research Center of Internet of Things Technology Applications(Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi 214122, China
  • 收稿日期:2020-11-19 修回日期:2020-12-30 接受日期:2021-02-04 出版日期:2021-06-22 发布日期:2021-06-30
  • 通讯作者: Hai-Lian Liang E-mail:lhl2010@jiangnan.edu.cn
  • 基金资助:
    Project supported by the National Natural Science Foundation of China (Grant No. 61504049).

Design and investigation of novel ultra-high-voltage junction field-effect transistor embedded with NPN

Xi-Kun Feng(冯希昆), Xiao-Feng Gu(顾晓峰), Qin-Ling Ma(马琴玲), Yan-Ni Yang(杨燕妮), and Hai-Lian Liang(梁海莲)†   

  1. Engineering Research Center of Internet of Things Technology Applications(Ministry of Education), Department of Electronic Engineering, Jiangnan University, Wuxi 214122, China
  • Received:2020-11-19 Revised:2020-12-30 Accepted:2021-02-04 Online:2021-06-22 Published:2021-06-30
  • Contact: Hai-Lian Liang E-mail:lhl2010@jiangnan.edu.cn
  • Supported by:
    Project supported by the National Natural Science Foundation of China (Grant No. 61504049).

RichHTML

1

PDF (PC)

97

赞

摘要： Ultra-high-voltage (UHV) junction field-effect transistors (JFETs) embedded separately with the lateral NPN (JFET-LNPN), and the lateral and vertical NPN (JFET-LVNPN), are demonstrated experimentally for improving the electrostatic discharge (ESD) robustness. The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-kV human body model (HBM) test. The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET. The failure analysis of the devices is performed with scanning electron microscopy, and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities. Finally, the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation, and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN, because the vertical NPN has a better electron collecting capacity. The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.

关键词: junction field-effect transistors, NPN, electrostatic discharge (ESD) robustness, ESD protection

Abstract: Ultra-high-voltage (UHV) junction field-effect transistors (JFETs) embedded separately with the lateral NPN (JFET-LNPN), and the lateral and vertical NPN (JFET-LVNPN), are demonstrated experimentally for improving the electrostatic discharge (ESD) robustness. The ESD characteristics show that both JFET-LNPN and JFET-LVNPN can pass the 5.5-kV human body model (HBM) test. The JFETs embedded with different NPNs have 3.75 times stronger in ESD robustness than the conventional JFET. The failure analysis of the devices is performed with scanning electron microscopy, and the obtained delayer images illustrate that the JFETs embedded with NPN transistors have good voltage endurance capabilities. Finally, the internal physical mechanism of the JFETs embedded with different NPNs is investigated with emission microscopy and Sentaurus simulation, and the results confirm that the JFET-LVNPN has stronger ESD robustness than the JFET-LNPN, because the vertical NPN has a better electron collecting capacity. The JFET-LVNPN is helpful in providing a strong ESD protection and functions for a power device.

Key words: junction field-effect transistors, NPN, electrostatic discharge (ESD) robustness, ESD protection

中图分类号:  (Semiconductor-device characterization, design, and modeling)

  • 85.30.De
85.30.Mn (Junction breakdown and tunneling devices (including resonance tunneling devices)) 73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))