中国物理B ›› 2019, Vol. 28 ›› Issue (8): 88501-088501.doi: 10.1088/1674-1056/28/8/088501

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇    下一篇

Improving robustness of GGNMOS with P-base layer for electrostatic discharge protection in 0.5-μm BCD process

Fei Hou(侯飞), Ruibo Chen(陈瑞博), Feibo Du(杜飞波), Jizhi Liu(刘继芝), Zhiwei Liu(刘志伟), Juin J Liou(刘俊杰)   

  1. 1 State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;
    2 School of Information Engineering, Zhengzhou University, Zhengzhou 450001, China
  • 收稿日期:2019-03-28 修回日期:2019-05-15 出版日期:2019-08-05 发布日期:2019-08-05
  • 通讯作者: Zhiwei Liu E-mail:ziv_liu@hotmail.com

Improving robustness of GGNMOS with P-base layer for electrostatic discharge protection in 0.5-μm BCD process

Fei Hou(侯飞)1, Ruibo Chen(陈瑞博)2, Feibo Du(杜飞波)1, Jizhi Liu(刘继芝)1, Zhiwei Liu(刘志伟)1, Juin J Liou(刘俊杰)2   

  1. 1 State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China;
    2 School of Information Engineering, Zhengzhou University, Zhengzhou 450001, China
  • Received:2019-03-28 Revised:2019-05-15 Online:2019-08-05 Published:2019-08-05
  • Contact: Zhiwei Liu E-mail:ziv_liu@hotmail.com

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摘要： Gate-grounded N-channel MOSFET (GGNMOS) has been extensively used for on-chip electrostatic discharge (ESD) protection. However, the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect. In this paper, an enhanced GGNMOS with P-base layer (PB-NMOS) are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer. TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices. All devices are fabricated in a 0.5-μm BCD process and measured using the transmission line pulsing (TLP) tester. Compared with the conventional GGNMOS, the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart, which can be increased by 15.38%. Furthermore, the PB-NMOS_type3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.

关键词: ESD, GGNMOS, failure current, trigger voltage

Abstract: Gate-grounded N-channel MOSFET (GGNMOS) has been extensively used for on-chip electrostatic discharge (ESD) protection. However, the ESD performance of the conventional GGNMOS is significantly degraded by the current crowding effect. In this paper, an enhanced GGNMOS with P-base layer (PB-NMOS) are proposed to improve the ESD robustness in BCD process without the increase in layout area or additional layer. TCAD simulations are carried out to explain the underlying mechanisms of that utilizing the P-base layer can effectively restrain the current crowing effect in proposed devices. All devices are fabricated in a 0.5-μm BCD process and measured using the transmission line pulsing (TLP) tester. Compared with the conventional GGNMOS, the proposed PB-NMOS devices offer a higher failure current than its conventional counterpart, which can be increased by 15.38%. Furthermore, the PB-NMOS_type3 possesses a considerably lower trigger voltage than the conventional GGNMOS to protect core circuit effectively.

Key words: ESD, GGNMOS, failure current, trigger voltage

中图分类号:  (Semiconductor-device characterization, design, and modeling)

  • 85.30.De