An improvement to computational efficiency of the drain current model for double-gate MOSFET

doi:10.1088/1674-1056/20/9/097304

中国物理B ›› 2011, Vol. 20 ›› Issue (9): 97304-097304.doi: 10.1088/1674-1056/20/9/097304

An improvement to computational efficiency of the drain current model for double-gate MOSFET

吴文¹, 赵巍¹, 周幸叶², 张健², 周致赜², 张立宁², 马晨月², 张兴²

(1)Peking University Shenzhen SOC Key Laboratory, PKU-HKUST Shenzhen Institution, Shenzhen 518057, China; (2)TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, China

收稿日期:2011-01-18 修回日期:2011-02-28 出版日期:2011-09-15 发布日期:2011-09-15

An improvement to computational efficiency of the drain current model for double-gate MOSFET

Zhou Xing-Ye(周幸叶)^a)b), Zhang Jian(张健)^a), Zhou Zhi-Ze(周致赜)^a), Zhang Li-Ning(张立宁)^a), Ma Chen-Yue(马晨月)^a), Wu Wen(吴文)^c), Zhao Wei(赵巍)^c), and Zhang Xing(张兴)^a)†

^a TSRC, Institute of Microelectronics, School of Electronic Engineering and Computer Science, Peking University, Beijing 100871, China; ^b Academy for Advanced Interdisciplinary Studies, Peking University, Beijing 100871, China; ^c Peking University Shenzhen SOC Key Laboratory, PKU-HKUST Shenzhen Institution, Shenzhen 518057, China

Received:2011-01-18 Revised:2011-02-28 Online:2011-09-15 Published:2011-09-15

摘要/Abstract

摘要： As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.

关键词: computational efficiency, compact model, double-gate, MOSFET

Abstract: As a connection between the process and the circuit design, the device model is greatly desired for emerging devices, such as the double-gate MOSFET. Time efficiency is one of the most important requirements for device modeling. In this paper, an improvement to the computational efficiency of the drain current model for double-gate MOSFETs is extended, and different calculation methods are compared and discussed. The results show that the calculation speed of the improved model is substantially enhanced. A two-dimensional device simulation is performed to verify the improved model. Furthermore, the model is implemented into the HSPICE circuit simulator in Verilog-A for practical application.

Key words: computational efficiency, compact model, double-gate, MOSFET

中图分类号: (Semiconductor-insulator-semiconductor structures)

73.40.Ty

73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator)) 61.44.Br (Quasicrystals)

周幸叶, 张健, 周致赜, 张立宁, 马晨月, 吴文, 赵巍, 张兴. An improvement to computational efficiency of the drain current model for double-gate MOSFET[J]. 中国物理B, 2011, 20(9): 97304-097304.

Zhou Xing-Ye(周幸叶), Zhang Jian(张健), Zhou Zhi-Ze(周致赜), Zhang Li-Ning(张立宁), Ma Chen-Yue(马晨月), Wu Wen(吴文), Zhao Wei(赵巍), and Zhang Xing(张兴) . An improvement to computational efficiency of the drain current model for double-gate MOSFET[J]. Chin. Phys. B, 2011, 20(9): 97304-097304.

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An improvement to computational efficiency of the drain current model for double-gate MOSFET

An improvement to computational efficiency of the drain current model for double-gate MOSFET

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