›› 2015, Vol. 24 ›› Issue (4): 47303-047303.doi: 10.1088/1674-1056/24/4/047303

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇    下一篇

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

马金荣, 乔明, 张波   

  1. State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
  • 收稿日期:2014-08-05 修回日期:2014-11-06 出版日期:2015-04-05 发布日期:2015-04-05

Novel substrate trigger SCR-LDMOS stacking structure for high-voltage ESD protection application

Ma Jin-Rong, Qiao Ming, Zhang Bo   

  1. State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China
  • Received:2014-08-05 Revised:2014-11-06 Online:2015-04-05 Published:2015-04-05
  • Contact: Qiao Ming E-mail:qiaoming@uestc.edu.cn

摘要: A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor (STSCR-LDMOS) stacked structure is proposed and simulated using the transimission line pulser (TLP) multiple-pulse simulation method in a 0.35-μm, 60-V biploar-CMOS-DMOS (BCD) process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metal-oxide semiconductor (SCR-LDMOS) in high-voltage electro-static discharge (ESD) protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

关键词: electrostatic discharge, high holding voltage, latch-up, STSCR-LDMOS

Abstract: A novel substrate trigger semiconductor control rectifier-laterally diffused metal-oxide semiconductor (STSCR-LDMOS) stacked structure is proposed and simulated using the transimission line pulser (TLP) multiple-pulse simulation method in a 0.35-μm, 60-V biploar-CMOS-DMOS (BCD) process without additional masks. On account of a very low holding voltage, it is susceptible to latch-up-like danger for the semiconductor control rectifier-laterally diffused metal-oxide semiconductor (SCR-LDMOS) in high-voltage electro-static discharge (ESD) protection applications. Although the conventional stacking structure has achieved strong latch-up immunity by increasing holding voltage, excessive high trigger voltage does not meet requirements for an ESD protection device. The holding voltage of the proposed stacked structure is proportional to the stacking number, whereas the trigger voltage remains nearly the same. A high holding voltage of 30.6 V and trigger voltage of 75.4 V are achieved.

Key words: electrostatic discharge, high holding voltage, latch-up, STSCR-LDMOS

中图分类号:  (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))

  • 73.40.Qv
85.30.De (Semiconductor-device characterization, design, and modeling) 85.30.Mn (Junction breakdown and tunneling devices (including resonance tunneling devices)) 85.30.Rs (Thyristors)