Key technologies for dual high-k and dual metal gate integration

doi:10.1088/1674-1056/27/9/097306

中国物理B ›› 2018, Vol. 27 ›› Issue (9): 97306-097306.doi: 10.1088/1674-1056/27/9/097306

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇下一篇

Key technologies for dual high-k and dual metal gate integration

Yong-Liang Li(李永亮), Qiu-Xia Xu(徐秋霞), Wen-Wu Wang(王文武)

Integrated Circuit Advanced Process Center, Institute of Microelectronics, Chinese Academy of Science, Beijing 100029, China

收稿日期:2018-06-04 修回日期:2018-07-03 出版日期:2018-09-05 发布日期:2018-09-05
通讯作者: Yong-Liang Li E-mail:liyongliang@ime.ac.cn
基金资助:
Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA010601).

Key technologies for dual high-k and dual metal gate integration

Yong-Liang Li(李永亮), Qiu-Xia Xu(徐秋霞), Wen-Wu Wang(王文武)

Integrated Circuit Advanced Process Center, Institute of Microelectronics, Chinese Academy of Science, Beijing 100029, China

Received:2018-06-04 Revised:2018-07-03 Online:2018-09-05 Published:2018-09-05
Contact: Yong-Liang Li E-mail:liyongliang@ime.ac.cn
Supported by:
Project supported by the National High Technology Research and Development Program of China (Grant No. 2015AA010601).

摘要/Abstract

摘要：

The key technologies for the dual high-k and dual metal gate, such as the electrical optimization of metal insert poly-Si stack structure, the separating of high-k and metal gate of n/pMOS in different regions of the wafer, and the synchronous etching of n/pMOS gate stack, are successfully developed. First, reasonable flat-band voltage and equivalent oxide thickness of pMOS MIPS structure are obtained by further optimizing the HfSiAlON dielectric through incorporating more Al-O dipole at interface between HfSiAlON and bottom SiO_x. Then, the separating of high-k and metal gate for n/pMOS is achieved by SC1 (NH₄OH:H₂O₂:H₂O=1:1:5) and DHF-based solution for the selective removing of nMOS TaN and HfSiON and by BCl₃-based plasma and DHF-based solution for the selective removing of pMOS TaN/Mo and HfSiAlON. After that, the synchronous etching of n/pMOS gate stack is developed by utilizing optimized BCl₃/SF₆/O₂/Ar plasma to obtain a vertical profile for TaN and TaN/Mo and by utilizing BCl₃/Ar plasma combined with DHF-based solution to achieve high selectivity to Si substrate. Finally, good electrical characteristics of CMOS devices, obtained by utilizing these new developed technologies, further confirm that they are practicable technologies for DHDMG integration.

关键词: high-k, metal gate, metal insert poly-Si stack (MIPS), dual high-k and dual metal gate (DHDMG) integration

Abstract:

Key words: high-k, metal gate, metal insert poly-Si stack (MIPS), dual high-k and dual metal gate (DHDMG) integration

中图分类号: (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))

73.40.Qv

73.50.Mx (High-frequency effects; plasma effects) 73.90.+f (Other topics in electronic structure and electrical properties of surfaces, interfaces, thin films, and low-dimensional structures)

李永亮, 徐秋霞, 王文武. Key technologies for dual high-k and dual metal gate integration[J]. 中国物理B, 2018, 27(9): 97306-097306.

Yong-Liang Li(李永亮), Qiu-Xia Xu(徐秋霞), Wen-Wu Wang(王文武). Key technologies for dual high-k and dual metal gate integration[J]. Chin. Phys. B, 2018, 27(9): 97306-097306.

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Key technologies for dual high-k and dual metal gate integration

Key technologies for dual high-k and dual metal gate integration

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