中国物理B ›› 2010, Vol. 19 ›› Issue (11): 117309-117309.doi: 10.1088/1674-1056/19/11/117309

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇    下一篇

An analytical threshold voltage model for dual-strained channel PMOSFET

秦珊珊, 张鹤鸣, 胡辉勇, 戴显英, 宣荣喜, 舒斌   

  1. Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China
  • 收稿日期:2009-12-16 修回日期:2010-07-22 出版日期:2010-11-15 发布日期:2010-11-15
  • 基金资助:
    Project supported by the National Defence Pre-research Foundation of China (Grant Nos. 51308040203, 9140A08060407DZ0103, and 6139801).

An analytical threshold voltage model for dual-strained channel PMOSFET

Qin Shan-Shan(秦珊珊)†, Zhang He-Ming(张鹤鸣), Hu Hui-Yong(胡辉勇), Dai Xian-Ying(戴显英), Xuan Rong-Xi(宣荣喜), and Shu Bin(舒斌)   

  1. Key Laboratory of Ministry of Education for Wide Band-Gap Semiconductor Materials and Devices, School of Microelectronics, Xidian University, Xi'an 710071, China
  • Received:2009-12-16 Revised:2010-07-22 Online:2010-11-15 Published:2010-11-15
  • Supported by:
    Project supported by the National Defence Pre-research Foundation of China (Grant Nos. 51308040203, 9140A08060407DZ0103, and 6139801).

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摘要： Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey(s-Si/s-SiGe/Si1-yGey) metal--oxide--semiconductor field-effect transistor (PMOSFET), analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si), because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor (MOSFET) designs.

Abstract: Based on the analysis of vertical electric potential distribution across the dual-channel strained p-type Si/strained Si1-xGex/relaxd Si1-yGey(s-Si/s-SiGe/Si1-yGey) metal–oxide–semiconductor field-effect transistor (PMOSFET), analytical expressions of the threshold voltages for buried channel and surface channel are presented. And the maximum allowed thickness of s-Si is given, which can ensure that the strong inversion appears earlier in the buried channel (compressive strained SiGe) than in the surface channel (tensile strained Si), because the hole mobility in the buried channel is higher than that in the surface channel. Thus they offer a good accuracy as compared with the results of device simulator ISE. With this model, the variations of threshold voltage and maximum allowed thickness of s-Si with design parameters can be predicted, such as Ge fraction, layer thickness, and doping concentration. This model can serve as a useful tool for p-channel s-Si/s-SiGe/Si1-yGey metal-oxide-semiconductor field-effect transistor (MOSFET) designs.

Key words: strained Si, strained SiGe, dual-channel metal–oxide–semiconductor field-effect transistor (MOSFET), threshold voltage

中图分类号:  (Semiconductor-device characterization, design, and modeling)

  • 85.30.De
85.30.Tv (Field effect devices)