The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

doi:10.1088/1674-1056/21/1/018501

中国物理B ›› 2012, Vol. 21 ›› Issue (1): 18501-018501.doi: 10.1088/1674-1056/21/1/018501

The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

赵远远, 乔明, 王伟宾, 王猛, 张波

State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

收稿日期:2011-06-17 修回日期:2011-07-18 出版日期:2012-01-15 发布日期:2012-01-20
基金资助:
Project supported by National Natural Science Foundation of China (Grant No. 60906038).

The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

Zhao Yuan-Yuan(赵远远)^†, Qiao Ming(乔明), Wang Wei-Bin(王伟宾), Wang Meng(王猛), and Zhang Bo(张波)

State Key Laboratory of Electronic Thin Films and Integrated Devices, University of Electronic Science and Technology of China, Chengdu 610054, China

Received:2011-06-17 Revised:2011-07-18 Online:2012-01-15 Published:2012-01-20
Supported by:
Project supported by National Natural Science Foundation of China (Grant No. 60906038).

摘要/Abstract

摘要： A high-side thin-layer silicon-on-insulator (SOI) pLDMOS is proposed, adopting field implant (FI) and multiple field plate (MFP) technologies. The breakdown mechanisms of back gate (BG) turn-on, surface channel punch-through, and vertical and lateral avalanche breakdown are investigated by setting up analytical models, simulating related parameters and verifying experimentally. The device structure is optimized based on the above research. The shallow junction achieved through FI technology attenuates the BG effect, the optimized channel length eliminates the surface channel punch-through, the advised thickness of the buried oxide dispels the vertical avalanche breakdown, and the MFP technology avoids premature lateral avalanche breakdown by modulating the electric field distribution. Finally, for the first time, a 300 V high-side pLDMOS is experimentally realized on a 1.5 μ m thick thin-layer SOI.

关键词: field implant technology, back gate punch-through, surface channel punch-through, avalanche breakdown

Abstract: A high-side thin-layer silicon-on-insulator (SOI) pLDMOS is proposed, adopting field implant (FI) and multiple field plate (MFP) technologies. The breakdown mechanisms of back gate (BG) turn-on, surface channel punch-through, and vertical and lateral avalanche breakdown are investigated by setting up analytical models, simulating related parameters and verifying experimentally. The device structure is optimized based on the above research. The shallow junction achieved through FI technology attenuates the BG effect, the optimized channel length eliminates the surface channel punch-through, the advised thickness of the buried oxide dispels the vertical avalanche breakdown, and the MFP technology avoids premature lateral avalanche breakdown by modulating the electric field distribution. Finally, for the first time, a 300 V high-side pLDMOS is experimentally realized on a 1.5 μ m thick thin-layer SOI.

Key words: field implant technology, back gate punch-through, surface channel punch-through, avalanche breakdown

中图分类号: (Semiconductor-device characterization, design, and modeling)

85.30.De

85.30.Tv (Field effect devices) 84.70.+p (High-current and high-voltage technology: power systems; power transmission lines and cables)

赵远远, 乔明, 王伟宾, 王猛, 张波. The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure[J]. 中国物理B, 2012, 21(1): 18501-018501.

Zhao Yuan-Yuan(赵远远), Qiao Ming(乔明), Wang Wei-Bin(王伟宾), Wang Meng(王猛), and Zhang Bo(张波) . The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure[J]. Chin. Phys. B, 2012, 21(1): 18501-018501.

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The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

The breakdown mechanism of a high-side pLDMOS based on a thin-layer silicon-on-insulator structure

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