Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors

doi:10.1088/1674-1056/24/12/128101

中国物理B ›› 2015, Vol. 24 ›› Issue (12): 128101-128101.doi: 10.1088/1674-1056/24/12/128101

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇下一篇

Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors

马刘红, 韩伟华, 王昊, 杨香, 杨富华

Engineering Research Center for Semiconductor Integration Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

收稿日期:2015-05-05 修回日期:2015-08-21 出版日期:2015-12-05 发布日期:2015-12-05
通讯作者: Han Wei-Hua, Yang Fu-Hua E-mail:weihua@semi.ac.cn;fhyang@semi.ac.cn
基金资助:
Project supported by the National Natural Science Foundation of China (Grant Nos. 61376096, 61327813, and 61404126) and the National Basic Research Program of China (Grant No. 2010CB934104).

Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors

Ma Liu-Hong (马刘红), Han Wei-Hua (韩伟华), Wang Hao (王昊), Yang Xiang (杨香), Yang Fu-Hua (杨富华)

Engineering Research Center for Semiconductor Integration Technology, Institute of Semiconductors, Chinese Academy of Sciences, Beijing 100083, China

Received:2015-05-05 Revised:2015-08-21 Online:2015-12-05 Published:2015-12-05
Contact: Han Wei-Hua, Yang Fu-Hua E-mail:weihua@semi.ac.cn;fhyang@semi.ac.cn
Supported by:
Project supported by the National Natural Science Foundation of China (Grant Nos. 61376096, 61327813, and 61404126) and the National Basic Research Program of China (Grant No. 2010CB934104).

摘要/Abstract

摘要： We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm²·V^-1·s^-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si-SiO₂ interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.

关键词: junctionless nanowire transistors, trap, femtosecond laser lithography, electron mobility

Abstract: We investigate the conductivity characteristics in the surface accumulation layer of a junctionless nanowire transistor fabricated by the femtosecond laser lithography on a heavily n-doped silicon-on-insulator wafer. The conductivity of the accumulation region is totally suppressed when the gate voltage is more positive than the flatband voltage. The extracted low field electron mobility in the accumulation layer is estimated to be 1.25 cm²·V^-1·s^-1. A time-dependent drain current measured at 6 K predicts the existence of a complex trap state at the Si-SiO₂ interface within the bandgap. The suppressed drain current and comparable low electron mobility of the accumulation layer can be well described by the large Coulomb scattering arising from the presence of a large density of interface charged traps. The effects of charge trapping and the scattering at interface states become the main reasons for mobility reduction for electrons in the accumulation region.

Key words: junctionless nanowire transistors, trap, femtosecond laser lithography, electron mobility

中图分类号: (Nanowires)

81.07.Gf

73.63.-b (Electronic transport in nanoscale materials and structures) 73.40.-c (Electronic transport in interface structures) 85.30.Tv (Field effect devices)

马刘红, 韩伟华, 王昊, 杨香, 杨富华. Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors[J]. 中国物理B, 2015, 24(12): 128101-128101.

Ma Liu-Hong (马刘红), Han Wei-Hua (韩伟华), Wang Hao (王昊), Yang Xiang (杨香), Yang Fu-Hua (杨富华). Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors[J]. Chin. Phys. B, 2015, 24(12): 128101-128101.

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Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors

Charge trapping in surface accumulation layer of heavily doped junctionless nanowire transistors

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