中国物理B ›› 2016, Vol. 25 ›› Issue (9): 97304-097304.doi: 10.1088/1674-1056/25/9/097304
• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇 下一篇
Jie Yu(于杰), Kun-ji Chen(陈坤基), Zhong-yuan Ma(马忠元), Xin-xin Zhang(张鑫鑫), Xiao-fan Jiang(江小帆), Yang-qing Wu(吴仰晴), Xin-fan Huang(黄信凡), Shunri Oda
Jie Yu(于杰)1, Kun-ji Chen(陈坤基)1, Zhong-yuan Ma(马忠元)1, Xin-xin Zhang(张鑫鑫)1, Xiao-fan Jiang(江小帆)1, Yang-qing Wu(吴仰晴)1, Xin-fan Huang(黄信凡)1, Shunri Oda2
摘要:
Based on the charge storage mode, it is important to investigate the scaling dependence of memory performance in silicon nanocrystal (Si-NC) nonvolatile memory (NVM) devices for its scaling down limit. In this work, we made eight kinds of test key cells with different gate widths and lengths by 0.13-μm node complementary metal oxide semiconductor (CMOS) technology. It is found that the memory windows of eight kinds of test key cells are almost the same of about 1.64 V @ ± 7 V/1 ms, which are independent of the gate area, but mainly determined by the average size (12 nm) and areal density (1.8×1011/cm2) of Si-NCs. The program/erase (P/E) speed characteristics are almost independent of gate widths and lengths. However, the erase speed is faster than the program speed of test key cells, which is due to the different charging behaviors between electrons and holes during the operation processes. Furthermore, the data retention characteristic is also independent of the gate area. Our findings are useful for further scaling down of Si-NC NVM devices to improve the performance and on-chip integration.
中图分类号: (Electronic structure of nanoscale materials and related systems)