A statistical RCL interconnect delay model taking account of process variations

doi:10.1088/1674-1056/20/1/018401

中国物理B ›› 2011, Vol. 20 ›› Issue (1): 18401-018401.doi: 10.1088/1674-1056/20/1/018401

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇下一篇

A statistical RCL interconnect delay model taking account of process variations

朱樟明, 万达经, 杨银堂, 恩云飞

Microelectronics School, Xidian University, Xi'an 710071, China

收稿日期:2010-03-30 修回日期:2010-08-23 出版日期:2011-01-15 发布日期:2011-01-15
基金资助:
Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066), the National Science &

A statistical RCL interconnect delay model taking account of process variations

Zhu Zhang-Ming(朱樟明)^†, Wan Da-Jing(万达经), Yang Yin-Tang(杨银堂), and En Yun-Fei(恩云飞)

Microelectronics School, Xidian University, Xi'an 710071, China

Received:2010-03-30 Revised:2010-08-23 Online:2011-01-15 Published:2011-01-15
Supported by:
Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066), the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005), and The National Key Laboratory Foundation (Grant No. ZHD200904).

摘要/Abstract

摘要： As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.

Abstract: As the feature size of the CMOS integrated circuit continues to shrink, process variations have become a key factor affecting the interconnect performance. Based on the equivalent Elmore model and the use of the polynomial chaos theory and the Galerkin method, we propose a linear statistical RCL interconnect delay model, taking into account process variations by successive application of the linear approximation method. Based on a variety of nano-CMOS process parameters, HSPICE simulation results show that the maximum error of the proposed model is less than 3.5%. The proposed model is simple, of high precision, and can be used in the analysis and design of nanometer integrated circuit interconnect systems.

Key words: process variation, interconnect line, statistical delay, successive linear approximation

中图分类号: (Electronic circuits)

84.30.-r

朱樟明, 万达经, 杨银堂, 恩云飞. A statistical RCL interconnect delay model taking account of process variations[J]. 中国物理B, 2011, 20(1): 18401-018401.

Zhu Zhang-Ming(朱樟明), Wan Da-Jing(万达经), Yang Yin-Tang(杨银堂), and En Yun-Fei(恩云飞). A statistical RCL interconnect delay model taking account of process variations[J]. Chin. Phys. B, 2011, 20(1): 18401-018401.

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A statistical RCL interconnect delay model taking account of process variations

A statistical RCL interconnect delay model taking account of process variations

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