中国物理B ›› 2010, Vol. 19 ›› Issue (12): 127805-127805.doi: 10.1088/1674-1056/19/12/127805

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇    下一篇

A novel low-swing interconnect optimization model with delay and bandwidth constraints

朱樟明, 郝报田, 杨银堂, 李跃进   

  1. Microelectronics School, Xidian University, Xi'an 710071, China
  • 收稿日期:2010-02-27 修回日期:2010-04-09 出版日期:2010-12-15 发布日期:2010-12-15
  • 基金资助:
    Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066), the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260), and the National Science &

A novel low-swing interconnect optimization model with delay and bandwidth constraints

Zhu Zhang-Ming(朱樟明)†, Hao Bao-Tian(郝报田), Yang Yin-Tang(杨银堂), and Li Yue-Jin(李跃进)   

  1. Microelectronics School, Xidian University, Xi'an 710071, China
  • Received:2010-02-27 Revised:2010-04-09 Online:2010-12-15 Published:2010-12-15
  • Supported by:
    Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60971066), the National High-Tech Program of China (Grant Nos. 2009AA01Z258 and 2009AA01Z260), and the National Science & Technology Important Project of China (Grant No. 2009ZX01034-002-001-005).

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摘要： Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing and adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor (CMOS) interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.

Abstract: Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing and adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor (CMOS) interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.

Key words: interconnect power, repeater area, low-swing circuit, time delay, bandwidth

中图分类号:  (Electronic circuits)

  • 84.30.-r
85.30.Tv (Field effect devices)