中国物理B ›› 2010, Vol. 19 ›› Issue (12): 127805-127805.doi: 10.1088/1674-1056/19/12/127805
• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇 下一篇
朱樟明, 郝报田, 杨银堂, 李跃进
Zhu Zhang-Ming(朱樟明)†, Hao Bao-Tian(郝报田), Yang Yin-Tang(杨银堂), and Li Yue-Jin(李跃进)
摘要: Interconnect power and repeater area are important in the interconnect optimization of nanometer scale integrated circuits. Based on the RLC interconnect delay model, by wire sizing, wire spacing and adopting low-swing interconnect technology, this paper proposed a power-area optimization model considering delay and bandwidth constraints simultaneously. The optimized model is verified based on 65-nm and 90-nm complementary metal-oxide semiconductor (CMOS) interconnect parameters. The verified results show that averages of 36% of interconnect power and 26% of repeater area can be saved under 65-nm CMOS process. The proposed model is especially suitable for the computer-aided design of nanometer scale systems-on-chip.
中图分类号: (Electronic circuits)