Abstract: Based on the hydrodynamic energy transport model, immunity from the hot-carrier effect in deep-sub-micron grooved-gate p-channel metal-oxide-semiconductor field-effect transistors (PMOSFETs) is analysed. The results show that hot carriers generated in grooved-gate PMOSFETs are much smaller than those in planar ones, especially for the case of channel lengths lying in the deep-sub-micron and super deep-sub-micron regions. Then, the hot-carrier generation mechanism and the reason why grooved-gate MOS devices can suppress the hot-carrier effect are studied from the viewpoint of physical mechanisms occurring in devices. It is found that the highest hot-carrier generating rate is at a medium gate bias voltage in three stress areas, similar to conventional planar devices. In deep-sub-micron grooved-gate PMOSFETs, the hot-carrier injection gate current is still composed mainly of the hot-electron injection current, and the hole injection current becomes dominant only at an extremely high gate voltage. In order to investigate other influences of the hot-carrier effect on the device characteristics, the degradation of the device performance is studied for both grooved-gate and planar devices at different interface states. The results show that the drift of the device electrical performance induced by the interface states in grooved-gate PMOSFETs is far larger than that in planar devices.

Key words: grooved-gate PMOSFETs, mechanism of hot-carrier generation, hot-carrier effect, interface states