中国物理B ›› 2006, Vol. 15 ›› Issue (10): 2297-2305.doi: 10.1088/1009-1963/15/10/018

• CLASSICAL AREAS OF PHENOMENOLOGY • 上一篇    下一篇

Low-parasitic ESD protection strategy for RF ICs in 0.35μm CMOS process

王　源, 贾　嵩, 陈中建, 吉利久   

  1. Institute of Microelectronics, Peking University, Beijing 100871, China
  • 收稿日期:2005-12-29 修回日期:2006-06-12 出版日期:2006-10-20 发布日期:2006-10-20

Low-parasitic ESD protection strategy for RF ICs in 0.35μm CMOS process

Wang Yuan(王源)†, Jia Song(贾嵩), Chen Zhong-Jian(陈中建), and Ji Li-Jiu(吉利久)   

  1. Institute of Microelectronics, Peking University, Beijing 100871, China
  • Received:2005-12-29 Revised:2006-06-12 Online:2006-10-20 Published:2006-10-20

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摘要： A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge (ESD) protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35\mum 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.

Abstract: A systemic and comprehensive ESD-induced parasitic model is presented in this paper, which is used to analyse the parasitic influences of electrostatic discharge (ESD) protection circuits on the performance of radio frequency applications. A novel low-parasitic ESD protection structure is made in a 0.35\mum 1P3M silicide CMOS process. The measured results show that this novel structure has a low parasitic capacitance about 310fF and a low leakage current about 12.2nA with a suitable ESD robustness target about 5kV human body model.

Key words: electrostatic discharge, radio frequency, parasitic capacitance, leakage current

中图分类号:  (Microwave integrated electronics)

  • 84.40.Lj
07.50.Hp (Electrical noise and shielding equipment)