中国物理B ›› 2023, Vol. 32 ›› Issue (8): 87701-087701.doi: 10.1088/1674-1056/acd524
Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack
Xiaoqing Sun(孙晓清)1,2, Hao Xu(徐昊)1,2, Junshuai Chai(柴俊帅)1,2, Xiaolei Wang(王晓磊)1,2, and Wenwu Wang(王文武)1,2,3,†
- 1. Key Laboratory of Microelectronics & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;
2. College of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China;
3. Bureau of Major R&D Programs Chinese Academy of Sciences, Beijing 100864, China
Charge trapping effect at the interface of ferroelectric/interlayer in the ferroelectric field effect transistor gate stack
Xiaoqing Sun(孙晓清)1,2, Hao Xu(徐昊)1,2, Junshuai Chai(柴俊帅)1,2, Xiaolei Wang(王晓磊)1,2, and Wenwu Wang(王文武)1,2,3,†
- 1. Key Laboratory of Microelectronics & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China;
2. College of Microelectronics, University of Chinese Academy of Sciences, Beijing 100049, China;
3. Bureau of Major R&D Programs Chinese Academy of Sciences, Beijing 100864, China
摘要： We study the charge trapping phenomenon that restricts the endurance of n-type ferroelectric field-effect transistors (FeFETs) with metal/ferroelectric/interlayer/Si (MFIS) gate stack structure. In order to explore the physical mechanism of the endurance failure caused by the charge trapping effect, we first establish a model to simulate the electron trapping behavior in n-type Si FeFET. The model is based on the quantum mechanical electron tunneling theory. And then, we use the pulsed Id-Vg method to measure the threshold voltage shift between the rising edges and falling edges of the FeFET. Our model fits the experimental data well. By fitting the model with the experimental data, we get the following conclusions. (i) During the positive operation pulse, electrons in the Si substrate are mainly trapped at the interface between the ferroelectric (FE) layer and interlayer (IL) of the FeFET gate stack by inelastic trap-assisted tunneling. (ii) Based on our model, we can get the number of electrons trapped into the gate stack during the positive operation pulse. (iii) The model can be used to evaluate trap parameters, which will help us to further understand the fatigue mechanism of FeFET.
中图分类号: (Ferroelectricity and antiferroelectricity)
- 77.80.-e