Silicon-on-insulator (SOI) is a widely used technique for power integrated circuits (PIC) because of its effective isolation, low leakage current, and high breakdown voltage (BV).^[1–3] Lateral double-diffused metal–oxide–semiconductor field-effect transistor (LDMOS) is a key device for the PIC, but it is not area efficient and suffers the contradiction between the BV and specific on-resistance R_on,sp. The BV of the power device is limited by the low lateral BV for the poor surface electric field distribution, and some work has been carried out, such as the variable lateral doping (VLD),^[4–7] super junction,^[8,9] and charge islands.^[10] Enhancing the electric field (ENDIF) of the dielectric buried layer is a feasible method to increase the vertical BV and several new structures have been developed^[11–15] in which introducing self-adaptive interface charges are effective and attractive.

In this paper, a stacked LDMOS with enhanced depletion effect by surface substrate is proposed. The additional surface substrate is formed of polysilicon, and the doping concentration in the drift region is increased based on the enhanced auxiliary depletion effect of the dual substrates, thus a lower R_on,sp is obtained. The multiple electric field peaks located in the surface dielectric trenches (SDT) modulate the bulk electric field distribution and improve the BV. The influences of the structure parameters on the BV and R_on,sp are analyzed.

Figure 1(a) shows the schematic cross-sectional view of the ST-LDMOS. The drift region is separated by the P buried layer to form two vertically parallel devices, and polysilicon and p-type silicon form the upper substrate and the lower substrate, respectively. The surface substrate enhances drift region depletion. Meanwhile it also enhances the compensation effect of the drift region, leading to the decrease of R_on,sp. Furthermore, many electric field peaks appear at the edge of the SDT, which prevents premature surface breakdown and increases the lateral BV. SDT parameter optimization is easy and the manufacturing process is simple.

Fig. 1.

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	Fig. 1. (a) Schematic cross section of the proposed ST-LDMOS; (b) the charge distribution at off-state (VDS > 0, VGS = 0).

Figure 1(b) gives the charge composition in the double dielectric trenches. According to the electric neutralization principle, the charge composition is expressed as

Table 1.

Table 1.

Table 1. Device parameters used in the simulation. . Device parameters ST-LDMOS C-LDMOS Drift length Ld/μm 24 24 Thickness of BOX/μm 1 1 Length of P-buried layer Lp/μm 10–40 – Height of oxide trench H/μm 0.25–0.75 – Width of oxide trench W/μm 0.5 – Spacing of oxide trench D/μm 0.5 – Buried concentration Np/cm−3 (2–4)×1016 –

Table 1. Device parameters used in the simulation. .

Figure 2(a) shows the equipotential contour distributions. The contours of the ST-LDMOS device present in a uniform manner, thus the BV reaches 459 V; while the optimal conventional device shows field crowding at the drain and source edges and the BV is limited to 259 V. In contrast with the C-LDMOS, the doping concentration of the ST-LDMOS is increased by an enhanced depletion effect from the surface substrate. Figure 2(b) shows the comparison of the off-state I–V characteristics between the C-LDMOS and ST-LDMOS, and the BV of the proposed device is greatly improved by 77.22%. The simulation results show that the proposed device has almost the same switching characteristics as the traditional Con device.

Fig. 2.

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	Fig. 2. (a) The equipotential contour distributions; (b) the off-state I–V and turn off time characteristics of the C-LDMOS and ST-LDMOS.

Figure 3 shows the lateral electric field distribution for the two LDMOSs. In Fig. 3(b), the ST-LDMOS shows a significant advantage over the optimal C-LDMOS. The lateral electric field of the ST-LDMOS is more uniform and its average is higher than that of the C-LDMOS because of the modulation effect by the multiple electric field peaks at the edge of the SDT in Fig. 3(b). According to the equivalent circuit of ST-LDMOS in Fig. 3(a), the on-resistance can be given as follows:

Fig. 3.

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	Fig. 3. Lateral electric field distribution at breakdown for two LDMOSs: (a) y = 0.001 μm, (b) y = 2.001 μm and y = 3.5 μm.

Figure 4(a) shows the vertical electric field and potential distributions. The electric field of the buried oxide layer (BOX), E_I, increases from 90 V/μm of the C-LDMOS to 400 V/μm, and BV of 796 V is obtained. More than 87.1% of BV is shared by the BOX for the ST-LDMOS, but only 55% for the C-LDMOS. In addition, the multiple electric field peaks increase the vertical electric field in SDT and modulate the electric field in the drift region, both result in the enhancement of the BV. Figure 4(b) shows the 3D electric field distribution of the ST-LDMOS, the voltage drop of SDT near the drain is the highest, and the electric field increases from the source to drain. The new electric field peak appears in the silicon layer and the lateral electric field is significantly improved.

Fig. 4.

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	Fig. 4. (a) Vertical electric field and potential distributions, (b) 3D electric field distribution of ST-LDMOS.

Figure 5(a) gives the relationship between the doping concentration N_d2 and BV with H = W = D = 0.5 μm, L_p = 20 μm, and t_p = 1 μm. The maximum BV increases with the increase of N_d2. The optimum N_d1 decreases with the increase of N_d2 as the sum of optimized doping concentration in the drift region is fixed. Figure 5(b) shows the relationship between the doping concentration N_d2 and R_on,sp, and the ratio of the doping concentration distribution is given by

Fig. 5.

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	Fig. 5. Influence of the drift region doping concentration on (a) BV and (b) Ron,sp.

Figure 6(a) shows the BV versus drift region doping concentration of the ST-LDMOS with P-buried length L_p as a parameter. The maximum of the BV decreases with the decrease of L_p, because when L_p is shorter, the electric field modulation is weaker. The R_on,sp reduces with the increase of N_d in Fig. 6(b) due to the enhancement of charge compensation effect, and the inset describes the relationship between the width (W_p) of the P-buried layer and R_on,sp. Figure 6(c) analyzes the influence of the P-buried position on the BV and R_on,sp. The optimum BV changes little within a small range of P-buried position, and the R_on,sp decreases with increasing P-buried position. The insertion table shows the effect of the P-buried diffusion process on the voltage.

Fig. 6.

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	Fig. 6. Influence of Nd on the BV and Ron,sp with different (a) Lp, (b) Wp, and (c) the P-buried position.

Figure 7 illustrates the influence of H on the BV and R_on,sp with L_p = 20 μm. The BV increases with increasing H, but R_on,sp is increased. The multiple electric field peaks increase with the increase of H, which is helpful to optimize the lateral electric field in the Si layer.

Fig. 7.

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	Fig. 7. BV and Ron,sp versus Nd with different H.

Figure 8(a) is a summary of R_on,sp versus BV for currently reported LDMOS devices^[16–20] and ST-LDMOS. It is noticeable that the proposed structure significantly relieves the trade-off between the BV and R_on,sp. Compared with the C-LDMOS with the same dimensions of L_d = 22.5 μm, the BV of the ST-LDMOS is increased by 77.22% due to the electric field modulation effect of the SDT. Furthermore, owing to the assisted-depletion effect of the double substrates, the optimal N_d and R_on,sp are greatly improved. Figure 8(b) is a summary of BV versus L_d for currently reported LDMOS devices.^[21,22] The ST-LDMOS exhibits the figure of merit (FOM) of 9.07 MW/cm², superior over the C-LDMOS and prior arts. There is little difference between the experimental data and the simulation data. The simulation uses the same model, so the simulation has certain reliability. The proposed structure is better than the conventional SOI LDMOS.

Fig. 8.

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	Fig. 8. (a) The Ron,sp versus BV relationship of the ST-LDMOS, (b) the BV versus Ld relationship.

The process simulation of the ST-LDMOS is shown in Fig. 9 by SILVACO. The starting material is a silicon wafer and the trench is etched. The SiO₂ is deposited and planarized. The trench substrate is created by the wafer bonding technology. A layer of high-quality 0.2 μm thick SiO₂ layer is thermally oxidized on the surface of the silicon groove, then repeatedly accumulated, so as to obtain SiO₂ with set thickness, good interface characteristics, and density. The bonding process is consistent with the conventional preparation process by using the planarization method combined with chemical mechanical polishing (CMP). The P-buried layer is formed by diffusion process. The remaining technology is compatible with the traditional CMOS process.

Fig. 9.

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	Fig. 9. Process simulation of ST-LDMOS.

A stacked LDMOS with enhanced depletion effect by surface substrate is proposed. Due to the electric field modulation effect in SDT, the proposed structure greatly increases the BV. The R_on,sp is improved based on the depletion enhancement of the double substrates. The ST-LDMOS exhibits an off state BV of 459 V and a R_on,sp of 23.24 mΩ·cm². The ST-LDMOS increases the BV by 77.22% and reduces the R_on,sp by 41.34% compared with the C-LDMOS. In addition, it reduces the size of the device and has potential applications in the PIC.