Three-dimensional global interconnect based on a design window

doi:10.1088/1674-1056/20/10/108401

中国物理B ›› 2011, Vol. 20 ›› Issue (10): 108401-108401.doi: 10.1088/1674-1056/20/10/108401

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇下一篇

Three-dimensional global interconnect based on a design window

钱利波, 朱樟明, 杨银堂

Microelectronics School, Xidian University, Xi'an 710071, China

收稿日期:2011-05-29 修回日期:2011-06-21 出版日期:2011-10-15 发布日期:2011-10-15
基金资助:
Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60676009) and the Natural Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2009ZX01034-002-001-005).

Three-dimensional global interconnect based on a design window

Qian Li-Bo(钱利波), Zhu Zhang-Ming(朱樟明)^†, and Yang Yin-Tang(杨银堂)

Microelectronics School, Xidian University, Xi'an 710071, China

Received:2011-05-29 Revised:2011-06-21 Online:2011-10-15 Published:2011-10-15
Supported by:
Project supported by the National Natural Science Foundation of China (Grant Nos. 60725415 and 60676009) and the Natural Science and Technology Major Project of the Ministry of Science and Technology of China (Grant No. 2009ZX01034-002-001-005).

摘要/Abstract

摘要： Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip (SOC) is established by evaluating the constraints of 1) wiring resource, 2) wiring bandwidth, and 3) wiring noise. In comparison to a two-dimensional integrated circuit (2D IC) in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.

Abstract: Based on a stochastic wire length distributed model, the interconnect distribution of a three-dimensional integrated circuit (3D IC) is predicted exactly. Using the results of this model, a global interconnect design window for a giga-scale system-on-chip (SOC) is established by evaluating the constraints of 1) wiring resource, 2) wiring bandwidth, and 3) wiring noise. In comparison to a two-dimensional integrated circuit (2D IC) in a 130-nm and 45-nm technology node, the design window expands for a 3D IC to improve the design reliability and system performance, further supporting 3D IC application in future integrated circuit design.

Key words: three-dimensional integrated circuit, design window, wiring resource, bandwidth

中图分类号: (Electronic circuits)

84.30.-r

84.30.Bv (Circuit theory)

钱利波, 朱樟明, 杨银堂. Three-dimensional global interconnect based on a design window[J]. 中国物理B, 2011, 20(10): 108401-108401.

Qian Li-Bo(钱利波), Zhu Zhang-Ming(朱樟明), and Yang Yin-Tang(杨银堂) . Three-dimensional global interconnect based on a design window[J]. Chin. Phys. B, 2011, 20(10): 108401-108401.

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Three-dimensional global interconnect based on a design window

Three-dimensional global interconnect based on a design window

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