Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

doi:10.1088/1674-1056/25/8/088502

中国物理B ›› 2016, Vol. 25 ›› Issue (8): 88502-088502.doi: 10.1088/1674-1056/25/8/088502

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇下一篇

Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

Zhi-Yuan Lun(伦志远), Yun Li(李云), Kai Zhao(赵凯), Gang Du(杜刚), Xiao-Yan Liu(刘晓彦), Yi Wang(王漪)

1 Institute of Microelectronics, Peking University, Beijing 100871, China;
2 School of Information and Communication, Beijing Information Science and Technology University, Beijing 100101, China

收稿日期:2016-03-05 修回日期:2016-04-12 出版日期:2016-08-05 发布日期:2016-08-05
通讯作者: Gang Du E-mail:gangdu@pku.edu.cn
基金资助:
Project supported by the National Natural Science Foundation of China (Grant Nos. 61404005, 61421005, and 91434201).

Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

Zhi-Yuan Lun(伦志远)¹, Yun Li(李云)¹, Kai Zhao(赵凯)², Gang Du(杜刚)¹, Xiao-Yan Liu(刘晓彦)¹, Yi Wang(王漪)¹

1 Institute of Microelectronics, Peking University, Beijing 100871, China;
2 School of Information and Communication, Beijing Information Science and Technology University, Beijing 100101, China

Received:2016-03-05 Revised:2016-04-12 Online:2016-08-05 Published:2016-08-05
Contact: Gang Du E-mail:gangdu@pku.edu.cn
Supported by:
Project supported by the National Natural Science Foundation of China (Grant Nos. 61404005, 61421005, and 91434201).

摘要/Abstract

摘要：

In this work, the trap-assisted tunneling (TAT) mechanism is modeled as a two-step physical process for charge trapping memory (CTM). The influence of the TAT mechanism on CTM performance is investigated in consideration of various trap positions and energy levels. For the simulated CTM structure, simulation results indicate that the positions of oxide traps related to the maximum TAT current contribution shift towards the substrate interface and charge storage layer interface during time evolutions in programming and retention operations, respectively. Lower programming voltage and retention operations under higher temperature are found to be more sensitive to tunneling oxide degradation.

关键词: trap assisted tunneling, charge trapping memory, tunneling oxide degradation

Abstract:

Key words: trap assisted tunneling, charge trapping memory, tunneling oxide degradation

中图分类号: (Semiconductor-device characterization, design, and modeling)

85.30.De

85.30.-z (Semiconductor devices)

伦志远, 李云, 赵凯, 杜刚, 刘晓彦, 王漪. Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level[J]. 中国物理B, 2016, 25(8): 88502-088502.

Zhi-Yuan Lun(伦志远), Yun Li(李云), Kai Zhao(赵凯), Gang Du(杜刚), Xiao-Yan Liu(刘晓彦), Yi Wang(王漪). Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level[J]. Chin. Phys. B, 2016, 25(8): 88502-088502.

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Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

Modeling of trap-assisted tunneling on performance of charge trapping memory with consideration of trap position and energy level

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