中国物理B ›› 2026, Vol. 35 ›› Issue (2): 28501-028501.doi: 10.1088/1674-1056/adecf9
Xiao Huang(黄潇)†, Peiwen Tong(童霈文)†, Qingjiang Li(李清江), Tuo Ma(马拓), Shuo Han(韩硕), Wei Wang(王伟)‡, and Yi Sun(孙毅)§
Xiao Huang(黄潇)†, Peiwen Tong(童霈文)†, Qingjiang Li(李清江), Tuo Ma(马拓), Shuo Han(韩硕), Wei Wang(王伟)‡, and Yi Sun(孙毅)§
摘要: Sensor noise is a critical factor that degrades the performance of image processing systems. In traditional computing systems, noise correction is implemented in the digital domain, resulting in redundant latency and power consumption overhead in the analog-to-digital conversion. In this work, we propose an analog-domain image correction architecture based on a proposed small-scale UNet, which implements a compact noise correction network within a one-transistor-one-memristor (1T1R) array. The statistical non-idealities of the fabricated 1T1R array (e.g., device variability) are rigorously incorporated into the network's training and inference simulations. This correction network architecture leverages memristors for conducting multiply-accumulate operations aimed at rectifying non-uniform noise, defective pixels (stuck-at-bright/dark), and exposure mismatch. Compared to systems without correction, the proposed architecture achieves up to 50.13 % improvement in recognition accuracy while demonstrating robust tolerance to memristor device-level errors. The proposed system achieves a 2.13-fold latency reduction and three orders of magnitude higher energy efficiency compared to conventional architecture. This work establishes a new paradigm for advancing the development of low-power, low-latency, and high-precision image processing systems.
中图分类号: (Nanoelectronic devices)