Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal-oxide-semiconductor devices

doi:10.1088/1674-1056/25/9/097101

中国物理B ›› 2016, Vol. 25 ›› Issue (9): 97101-097101.doi: 10.1088/1674-1056/25/9/097101

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇下一篇

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal-oxide-semiconductor devices

1. School of Microelectronics, Xidian University, Key Laboratory of Wide Band Gap Semiconductor Materials and Devices, Xi'an 710071, China;
2. Global Energy Interconnection Research Institute, Beijing 102209, China;
3. School of Advanced Materials and Nanotechnology, Xidian University, Xi'an 710071, China;
4. Zhuzhou CRRC Times Electric Company Limited, Zhuzhou 412001, China;
5. Zhongxing Telecommunication Equipment Corporation, Shenzhen 518057, China

收稿日期:2016-01-07 修回日期:2016-04-15 出版日期:2016-09-05 发布日期:2016-09-05
通讯作者: Hongliang Lv, Xiaoyan Tang E-mail:hllv@mail.xidian.edu.cn;xytang@xidian.edu.cn
基金资助:
Project supported by the National Natural Science Foundation of China (Grant Nos. 61404098 and 61274079), the Doctoral Fund of Ministry of Education of China (Grant No. 20130203120017), the National Key Basic Research Program of China (Grant No. 2015CB759600), the National Grid Science & Technology Project, China (Grant No. SGRI-WD-71-14-018), and the Key Specific Project in the National Science & Technology Program, China (Grant Nos. 2013ZX02305002-002 and 2015CB759600).

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal-oxide-semiconductor devices

Yifan Jia(贾一凡)¹, Hongliang Lv(吕红亮)¹, Yingxi Niu(钮应喜)², Ling Li(李玲)², Qingwen Song(宋庆文)^1,3, Xiaoyan Tang(汤晓燕)¹, Chengzhan Li(李诚瞻)⁴, Yanli Zhao(赵艳黎)⁴, Li Xiao(肖莉)⁵, Liangyong Wang(王梁永)⁵, Guangming Tang(唐光明)⁵, Yimen Zhang(张义门)¹, Yuming Zhang(张玉明)¹

1. School of Microelectronics, Xidian University, Key Laboratory of Wide Band Gap Semiconductor Materials and Devices, Xi'an 710071, China;
2. Global Energy Interconnection Research Institute, Beijing 102209, China;
3. School of Advanced Materials and Nanotechnology, Xidian University, Xi'an 710071, China;
4. Zhuzhou CRRC Times Electric Company Limited, Zhuzhou 412001, China;
5. Zhongxing Telecommunication Equipment Corporation, Shenzhen 518057, China

Received:2016-01-07 Revised:2016-04-15 Online:2016-09-05 Published:2016-09-05
Contact: Hongliang Lv, Xiaoyan Tang E-mail:hllv@mail.xidian.edu.cn;xytang@xidian.edu.cn
Supported by:
Project supported by the National Natural Science Foundation of China (Grant Nos. 61404098 and 61274079), the Doctoral Fund of Ministry of Education of China (Grant No. 20130203120017), the National Key Basic Research Program of China (Grant No. 2015CB759600), the National Grid Science & Technology Project, China (Grant No. SGRI-WD-71-14-018), and the Key Specific Project in the National Science & Technology Program, China (Grant Nos. 2013ZX02305002-002 and 2015CB759600).

摘要/Abstract

摘要： The effect of nitric oxide (NO) annealing on charge traps in the oxide insulator and transition layer in n-type 4H-SiC metal-oxide-semiconductor (MOS) devices has been investigated using the time-dependent bias stress (TDBS), capacitance-voltage (C-V), and secondary ion mass spectroscopy (SIMS). It is revealed that two main categories of charge traps, near interface oxide traps (N_niot) and oxide traps (N_ot), have different responses to the TDBS and C-V characteristics in NO-annealed and Ar-annealed samples. The N_niot are mainly responsible for the hysteresis occurring in the bidirectional C-V characteristics, which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor. However, N_ot is mainly responsible for the TDBS induced C-V shifts. Electrons tunneling into the N_ot are hardly released quickly when suffering TDBS, resulting in the problem of the threshold voltage stability. Compared with the Ar-annealed sample, N_niot can be significantly suppressed by the NO annealing, but there is little improvement of N_ot. SIMS results demonstrate that the N_niot are distributed within the transition layer, which correlated with the existence of the excess silicon. During the NO annealing process, the excess Si atoms incorporate into nitrogen in the transition layer, allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of N_niot.

关键词: 4H-SiC metal-oxide-semiconductor devices, NO annealing, near interface oxide traps, oxide traps

Abstract: The effect of nitric oxide (NO) annealing on charge traps in the oxide insulator and transition layer in n-type 4H-SiC metal-oxide-semiconductor (MOS) devices has been investigated using the time-dependent bias stress (TDBS), capacitance-voltage (C-V), and secondary ion mass spectroscopy (SIMS). It is revealed that two main categories of charge traps, near interface oxide traps (N_niot) and oxide traps (N_ot), have different responses to the TDBS and C-V characteristics in NO-annealed and Ar-annealed samples. The N_niot are mainly responsible for the hysteresis occurring in the bidirectional C-V characteristics, which are very close to the semiconductor interface and can readily exchange charges with the inner semiconductor. However, N_ot is mainly responsible for the TDBS induced C-V shifts. Electrons tunneling into the N_ot are hardly released quickly when suffering TDBS, resulting in the problem of the threshold voltage stability. Compared with the Ar-annealed sample, N_niot can be significantly suppressed by the NO annealing, but there is little improvement of N_ot. SIMS results demonstrate that the N_niot are distributed within the transition layer, which correlated with the existence of the excess silicon. During the NO annealing process, the excess Si atoms incorporate into nitrogen in the transition layer, allowing better relaxation of the interface strain and effectively reducing the width of the transition layer and the density of N_niot.

Key words: 4H-SiC metal-oxide-semiconductor devices, NO annealing, near interface oxide traps, oxide traps

中图分类号: (Semiconductor compounds)

71.20.Nr

73.40.Qv (Metal-insulator-semiconductor structures (including semiconductor-to-insulator)) 73.50.Gr (Charge carriers: generation, recombination, lifetime, trapping, mean free paths) 61.72.Cc (Kinetics of defect formation and annealing)

贾一凡, 吕红亮, 钮应喜, 李玲, 宋庆文, 汤晓燕, 李诚瞻, 赵艳黎, 肖莉, 王梁永, 唐光明, 张义门, 张玉明. Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal-oxide-semiconductor devices[J]. 中国物理B, 2016, 25(9): 97101-097101.

Yifan Jia(贾一凡), Hongliang Lv(吕红亮), Yingxi Niu(钮应喜), Ling Li(李玲), Qingwen Song(宋庆文), Xiaoyan Tang(汤晓燕), Chengzhan Li(李诚瞻), Yanli Zhao(赵艳黎), Li Xiao(肖莉), Liangyong Wang(王梁永), Guangming Tang(唐光明), Yimen Zhang(张义门), Yuming Zhang(张玉明). Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal-oxide-semiconductor devices[J]. Chin. Phys. B, 2016, 25(9): 97101-097101.

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Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal-oxide-semiconductor devices

Effect of NO annealing on charge traps in oxide insulator and transition layer for 4H-SiC metal-oxide-semiconductor devices

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