中国物理B ›› 2010, Vol. 19 ›› Issue (11): 110202-110304.doi: 10.1088/1674-1056/19/11/110202

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Statistical Elmore delay of RC interconnect tree

董刚, 杨杨, 柴常春, 杨银堂   

  1. Microelectronics Institute, Xidian University, Xi'an 710071, China
  • 收稿日期:2009-12-09 修回日期:2010-04-27 出版日期:2010-11-15 发布日期:2010-11-15
  • 基金资助:
    Project supported by the National Natural Science Foundation of China (Grant No. 60606006), the National Science Fund for Distinguished Young Scholars of China (Grant No. 60725415), and the Basic Science Research Fund in Xidian University, China.

Statistical Elmore delay of RC interconnect tree

Dong Gang(董刚), Yang Yang(杨杨), Chai Chang-Chun(柴常春), and Yang Yin-Tang(杨银堂)   

  1. Microelectronics Institute, Xidian University, Xi'an 710071, China
  • Received:2009-12-09 Revised:2010-04-27 Online:2010-11-15 Published:2010-11-15
  • Supported by:
    Project supported by the National Natural Science Foundation of China (Grant No. 60606006), the National Science Fund for Distinguished Young Scholars of China (Grant No. 60725415), and the Basic Science Research Fund in Xidian University, China.

摘要: As feature size keeps scaling down, process variations can dramatically reduce the accuracy in the estimation of interconnect performance. This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations. The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation. Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given fluctuation range of interconnect geometric parameters. Experimental results demonstrate that the approach matches well with Monte Carlo simulations. The errors of proposed mean and standard deviation are less than 1% and 7%, respectively. Simulations prove that our model is efficient and accurate.

Abstract: As feature size keeps scaling down, process variations can dramatically reduce the accuracy in the estimation of interconnect performance. This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations. The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation. Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given fluctuation range of interconnect geometric parameters. Experimental results demonstrate that the approach matches well with Monte Carlo simulations. The errors of proposed mean and standard deviation are less than 1% and 7%, respectively. Simulations prove that our model is efficient and accurate.

Key words: statistical delay, parasitic extraction, RC interconnect, process variations

中图分类号:  (Geometry, differential geometry, and topology)

  • 02.40.-k
02.50.Ng (Distribution theory and Monte Carlo studies) 05.40.-a (Fluctuation phenomena, random processes, noise, and Brownian motion) 84.30.Bv (Circuit theory)