中国物理B ›› 2010, Vol. 19 ›› Issue (11): 110202-110304.doi: 10.1088/1674-1056/19/11/110202
董刚, 杨杨, 柴常春, 杨银堂
Dong Gang(董刚)†, Yang Yang(杨杨), Chai Chang-Chun(柴常春), and Yang Yin-Tang(杨银堂)
摘要: As feature size keeps scaling down, process variations can dramatically reduce the accuracy in the estimation of interconnect performance. This paper proposes a statistical Elmore delay model for RC interconnect tree in the presence of process variations. The suggested method translates the process variations into parasitic parameter extraction and statistical Elmore delay evaluation. Analytical expressions of mean and standard deviation of interconnect delay can be obtained in a given fluctuation range of interconnect geometric parameters. Experimental results demonstrate that the approach matches well with Monte Carlo simulations. The errors of proposed mean and standard deviation are less than 1% and 7%, respectively. Simulations prove that our model is efficient and accurate.
中图分类号: (Geometry, differential geometry, and topology)