Thermal resistance matrix representation of thermal effects and thermal design of microwave power HBTs with two-dimensional array layout
Faculty of Information Technology, Beijing University of Technology, Beijing 100124, China
† Corresponding author. E-mail:
dyjin@bjut.edu.cn
1. IntroductionIn recent years, heterojunction bipolar transistors (HBTs) array with parallel HBT cells layout has been used widely for microwave power applications[1–4] due to its high current handling capability.[5–7] However, the self-heating effect caused by the power dissipation of each HBT cell and the thermal coupling effect among the adjacent HBT cells result in an uneven temperature profile in the HBTs array. Because of the positive temperature coefficient of the emitter current, the central HBT cells with higher temperature will conduct more current and consequently generate more heat, which aggravates the thermal effects and leads to thermal breakdown or thermal runaway.[8,9]
In order to obtain more uniform temperature distribution and tackle these thermal issues, one-dimensional (along emitter width direction) layout design technologies including variation of emitter length in HBT cells[10,11] (in Fig. 1(a)) and variation of emitter spacing between HBT cells[12–15] (in Fig. 1(b)) are used widely, which could decrease the temperature difference along the emitter width direction. However, there is still a higher temperature in the center of each emitter. At the same time, the non-uniformity of the temperature profile along the emitter length direction is not reduced. In recent research, the technology of multi-emitter array (in Fig. 1(c)) is proposed to decrease the temperature difference along the emitter length direction effectively,[16,17] which shows the superior thermal properties of the HBTs array with two-dimensional parallel HBT cells layout (2-D HBTs array). However, the layout design methodology of 2-D HBTs array has not been studied.
It is known that the thermal resistance matrix ([Rij]) could be used to represent the thermal effects of a one-dimensional HBT array,[18,19] which is helpful to design the layout of the device. However, the prior [Rij] representation is not applicable for the 2-D HBTs array.
In this paper, with the aid of the thermal network of a 2-D HBTs array, a new thermal resistance matrix ([Rijkl]) is proposed, including self-heating thermal resistance (Rijij) in the (i, j) HBT cell and thermal coupling resistance (
to represent the self-heating and thermal coupling effects, respectively. The dependence of [Rijkl] on cell spacing along the emitter length direction (Sx) and cell spacing along the emitter width direction (Sy) is also studied respectively. Furthermore, with the aid of [Rijkl], the HBTs array with a novel 2-D non-uniform cell spacing layout (including non-uniform Sx and non-uniform
is designed to lower the peak junction temperature, reduce the non-uniformity of the temperature profile, and hence alleviate the thermal issues of the HBTs array.
2. Thermal-electrical modelTo account for the self-heating and the thermal coupling effects, a thermal network of 2-D HBTs array (N × M HBT cells) with a ground-referenced thermal voltage is shown in Fig. 2, where each HBT cell is assigned with a constant temperature (e.g., its average temperature).
For the (i, j) HBT cell in the thermal network, the self-heating effect can be represented as a parallel combination of Rijij and dissipated power (Pij). The self-heating temperature rise of the (i, j) HBT cell (
) is obtained as
. Meanwhile, the thermal coupling effect can be represented as a series thermal coupling voltage, which is a combination of the temperature rise caused by the rest HBT cells. The thermal coupling temperature rise of the (i, j) HBT cell (
) is obtained as
where
Rijkl represents the contribution of the (
k,
l) HBT cell to the temperature rise of the (
i,
j) HBT cell,
Pkl represents the dissipated power of the (
k,
l) HBT cell (
),
is the collector current of the (
k,
l) HBT cell, and
VCE is the collector–emitter voltage.
Therefore, the peak junction temperature of the (i, j) HBT cell (Tij) including the self-heating temperature rise and the total thermal coupling temperature rise is obtained as
For the 2-D HBTs array with
N ×
M HBT cells, [
Rijkl] is expressed as
It is noted that there are
N ×
M sub-thermal resistance matrices in [
Rijkl], including
, where
can be expressed as
In this paper, the thermal model of the strained Si/SiGe HBTs array is established with ANSYS. The electrical model is established with MATLAB, which has considered the positive temperature coefficient of the collector current in each HBT cell
where
is the collector current of the (
i,
j) HBT cell,
is the saturation current,
k is Boltzmann’s constant,
q is the charge of electron,
is the base–emitter voltage, and
ϕ is the negative temperature coefficient of
.
As a result, the thermal-electrical model is established based on the iterative solution between ANSYS and MATLAB, and the temperature of the HBTs array (with N × M HBT cells) is first calculated under the same power level. By increasing the power of the (k, l) HBT cell (
), a new temperature distribution is calculated. Therefore, [Rijkl] including Rijij and
is obtained by using the temperature rise of the (i, j) HBT cell (
) as
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2.1. Impact of cell spacing along emitter length directionTake a 2 × 1 HBTs array for example, [Rijkl] is calculated, and the impact of cell spacing along the emitter length direction (Sx) on the thermal characteristics of the HBTs array is studied. The layout of the 2 × 1 HBTs array is shown in Fig. 3, where both the chip width (W) and the chip length (L) is
, the width (w) and the length (l) of each HBT cell is
and
, respectively.
The impact of Sx on Rijij and
is shown in Figs. 4 and 5, respectively. It can be seen that Rijij decreases as Sx increases from
to
due to the increase of the heat dissipation path. However, Rijij increases exponentially when Sx increases beyond
. It is because both the front-edge and back-edge surfaces of the chip along the emitter length direction are adiabatic, which restrict the lateral spread of the heat flow spread from the heat source to the outside. Different from Rijij,
keeps decreasing as Sx increases, and the trend of
can be approximated by an exponential function, indicating that the effective thermal coupling exists when two cells are very close to each other.
The impact of Sx on the peak junction temperature (Tij) at IC of 0.4 mA and VCE of 5 V is shown in Fig. 6, where the trend of Tij is almost the same as that of Rijij. It is because
is far less than Rijij in the [Rijkl] of the given 2 × 1 HBTs array and the trend of Tij is mainly determined by Rijij.
2.2. Impact of cell spacing along emitter width directionTake a 1 × 2 HBTs array for example, [Rijkl] is calculated, and the impact of cell spacing along the emitter width direction (Sy) on the thermal characteristics of the HBTs array is studied. The layout of the 1 × 2 HBTs array is shown in Fig. 7, where both the chip size and the size of each HBT cell is the same as those of the 2 × 1 HBTs array. Sy is the cell spacing along the emitter width direction.
The impact of Sy on Rijij and
is shown in Figs. 8 and 9, respectively. It can be seen that Rijij decreases linearly as Sy increases from
to
, and increases exponentially when Sy increases beyond
. It is because the lateral spread of heat flow is restricted by the left and right edges of the chip and the spreading angle of the heat flow is decreased, which decrease the heat dissipation path and lead to the increase of Rijij. At the same time,
keeps decreasing exponentially as Sy increases.
Figure 10 shows the impact of Sy on Tij at IC of 0.4 mA and VCE of 5 V, where Tij decreases with a parabola distribution as Sy increases from
to
, and remains approximately constant when Sy increases beyond
. It is because
is in the same order with Rijij, and hence both
and Rijij will affect the thermal characteristics of the HBTs array.
From this analysis, it can be concluded that both Sx and Sy should be designed carefully to effectively decrease Rijij and
. The decrease of Rijij and
is helpful for lowering the peak junction temperature of HBTs array, which sheds light on adopting a 2-D non-uniform cell spacing layout to improve the thermal characteristics of HBTs array.
3. Thermal-electrical model verificationTake a HBTs array with 1 × 20 HBT cells for example, both the simulated temperature profile along the central line across the HBT cells and the measured temperature profile reported in Ref. [15] are shown in Fig. 11. The simulated temperature profile matches well with the measured data, verifying the thermal-electrical model used in the simulations.
4. Layout designWith the aid of the thermal-electrical model, [Rijkl] of a 2 × 6 HBTs array (array-1) with uniform cell spacings of
along the emitter length direction and
along the emitter width direction is calculated at IC of 2.4 mA and VCE of 5 V
The detail profile of [Rijkl] in array-1 is shown in Fig. 12.
At the same time, iterations are used to calculate Tij and Pkl of array-1. First, it is assumed that there is an even collector current distribution across all HBT cells. Due to the thermal effects, the temperature of each HBT cell can be calculated with a temperature rise different from the others’. Because of the positive temperature coefficient of
in Eq. (5), the collector current (
) as well as the dissipated power (Pkl) of each HBT cell is redistributed and leads to a new distribution of Tij. The above steps are iterated until the final steady-state solutions are achieved. The steady-state results of Pkl in array-1 are shown in Fig. 13. The temperature profile of array-1 is shown in Fig. 14.
In order to improve the uniformity of the Pkl distribution and lower the temperature of the central HBT cells, both of cell spacing along the emitter length direction (Sx) and cell spacing along the emitter width direction (Sy) are designed carefully. For Sx, the spacings between the central cells should be increased significantly to lower Rijij, because
is far less than Rijij for the cells along the emitter length direction and the temperature difference is mainly determined by Rijij. For
the spacings between the central cells are increased moderately to lower both Rijij and
. It is because
is in the same order with Rijij for the cells along the emitter width direction and the temperature difference is determined by both Rijij and
. Moreover, the temperature difference will remain approximately constant as Sy increase to a certain distance. At the same time, considering that the outside cells are more convenient to spread heat, both Sx and Sy of the outside cells can be decreased to keep the total cell spacing unchanged. A 2 × 6 HBTs array (array-2) with non-uniform Sx and non-uniform Sy is designed under the same power density of array-1. The detail values of Sx and Sy of the two types of HBTs arrays are presented in Tables 1 and 2, respectively. The layouts of the two types of HBTs arrays are also presented in Fig. 15. Array-2 also has an identical vertical structure, total emitter area, and total cell spacing to those of array-1. The detail profile of [Rijkl] in array-2 is shown in Fig. 16. For array-2, not only Rijij of each HBT cell but also
in the central HBT cells decrease obviously, when compared with those of array-1. Take the central (1, 3) HBT cell for example,
of the two types of HBTs arrays is respectively given by
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It is shown that
R1313 is lowered by 5476 K/W with an improvement of 13.4% and
is also improved from 8.5% to 43.7%.
Table 1.
Table 1.
| Table 1.
Cell spacing along emitter length direction of the two types of HBTs arrays.
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Table 2.
Table 2.
| Table 2.
Cell spacing along emitter width direction of the two types of HBTs arrays.
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The correlated Pkl and the temperature profile of array-2 are shown in Figs. 17 and 18, respectively. For array-2, the maximum power level difference of the HBT cells is decreased by 38.7% when compared with that of array-1. As a result, array-2 has a lower peak junction temperature of 407.7 K, which is lowered by 4.2% and the uniformity of the cell temperature is improved by 46.9%.
As the collector–emitter voltage VCE is increased to 7 V, the calculated correlated Pkl and Tij of the HBT cells in the two arrays are shown in Figs. 19 and 20, respectively. For array-2, the maximum power level difference is decreased by 36.5%, the peak junction temperature is lowered by 20.2 K, and the uniformity of the cell temperature is improved by 52.7%, when compared with those of array-1. It indicates that, for the HBTs array with designed non-uniform cell spacing, the high power-handling capability and thermal dissipation capability are kept when VCE increases.
5. ConclusionTo represent the self-heating effect and thermal coupling effect of the HBTs array with N × M HBT cells, [Rijkl] including Rijij and
is presented in this paper. With the aid of a thermal network, the thermal-electrical model is established based on the iterative solution between ANSYS and MATLAB, and [Rijkl] of the HBTs array are calculated. The dependence of [Rijkl] and peak junction temperature Tij on cell spacing (Sx and Sy) is also investigated. For HBT cells along the emitter length direction, Tij decreases as Sx increases from
to
, and Tij increases exponentially when Sx increases beyond
. The trend of Tij versus Sx is mainly determined by the variation of Rijij. However, for HBT cells along the emitter width direction, Tij decreases as Sy increases from
to
, and Tij remains approximately constant when Sy increases beyond
, where the trend of Tij versus Sy is determined by both Rijij and
. As a result, the moderate increase of Sx and Sy could effectively lower Rijij and
as well as Tij. Furthermore, by taking a 2 × 6 HBTs array for example, the 2-D non-uniform cell spacing layout (including non-uniform Sx and non-uniform
is designed. For the optimized HBTs array, the peak junction temperature is lowered by 4.2%, the uniformity of the cell temperature is improved by 46.9%, and the maximum power level difference of the HBT cells is decreased by 38.7%, when compared with those of the uniform device. At the same time, the high power-handling capability and thermal dissipation capability are kept as VCE increases from 5 V to 7 V, indicating that the 2-D non-uniform cell spacing layout is a useful method to design power HBTs arrays for high thermal stability.