The PPD CMOS APS was a scientific image sensor with 2048 by 2040 pixels, manufactured using 0.18-μm standard CMOS technology. The sensor was operated in rolling shutter mode. Figure 1 shows the schematic of a PPD 4T pixel with the cross-section of the photo-sensing element, a charge transfer gate (TG), and floating diffusion (FD). The gate oxide thickness is 7 nm and the thickness of shallow trench isolation (STI) surrounding the PDD is around 360 nm. As can be seen, the photo-sensing element consists of two p–n junctions: the p⁺/n junction close to the surface and the n/p-sub junction in the silicon bulk. As shown in the figure, the photo-electrons are generated and collected in the PPD during the exposure time. After that, the FD needs to be reset first to remove any redundant charges. In the end, the TG is switched on so that the electrons stored in the PPD flow to the FD, and are subsequently read-out through a source follower (SF). V_OFF is the voltage applied to the TG when the TG is switched off with a nominal 0 V. This region of pixels is considered to be the most vulnerable to the effects of radiation.

Fig. 1.

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	Fig. 1. (color online) Schematic diagram of PPD 4T pixel.

Considering that a sensor has 400 million pixel unites, a sample has been exposed to ⁶⁰Co gamma ray up to 100 krad (SiO₂) at a dose rate of 50 rad (SiO₂)/s. During the irradiation, the sensor was unbiased with all pins grounded, and gamma irradiation was performed using ⁶⁰Co gamma source at the Xinjiang Technical Institute of Physics and Chemistry in Urumqi, China. All parameters were measured immediately after irradiation at room temperature (around 23 °C) in the case of annealing.

In order to discriminate the contributions of the two kinds of defects, trapped oxide charges and interface states, after gamma irradiation, annealing tests at 100 °C and 200 °C for 168 hours were performed, respectively.

The dark signal is defined as the carriers generated in the potential wells under the pixel in fully dark conditions. Figure 2 shows the degradation of the dark current as a function of the total dose. It increases with the TID increasing as expected.

Fig. 2.

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	Fig. 2. Variation of dark current with total ionizing dose.

When an APS is irradiated by gamma rays and protons, several mechanisms induce the dark current to increase. Displacement damage produced by gamma rays is negligible, leading to the bulk dark current remaining unchanged. Damages can cause a build-up of traps at the interface (usually called Si/SiO₂ interface traps), which induces the current to increase near the depleted region in the photodiode. As a consequence, trapped oxide charges will change the distribution of the electric field and modify the Si/SiO₂ interface potential, which can cause the depletion region to extend and thus strongly affecting the generation rate of the charge in the neutral state. The distribution of the origin of dark current in PPD CMOS APS has been proposed in previous work^[8–10] and is shown in Fig. 3. The first source of dark current is that the current comes from the transfer gate where the depletion region is close to the interface, in which the generation of interface states increases the dark current.^[8] The second source is that the current comes from the STI surrounding the photodiode as presented in Ref. [9]. The last one, which was presented in Ref. [10], is that at high total dose (i.e., above 300 krad (SiO₂)), the dielectric above the pinned-photodiode is involved.

Fig. 3.

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	Fig. 3. Dark current generation mechanism after irradiation with γ-ray.

In this paper, we simply distinguish the contributions of the different origins of dark current. We believe that the dark current coming from the dielectric can be ignored after the highest TID only at 100 krad (SiO₂). The main sources come from the interface states located at TG and STI, which surround the PPD. The number of dark electrons from the TG edge strongly depends on the bias. When V_OFF is set to be at negative bias, the TG is accumulated with holes which recombine with dark electrons generated from interface defects and fill the traps caused by γ -irradiation around the TG.^[11] If the dark current generated in the TG is suppressed by using a negative bias, the remaining dark current mainly comes from STI.

As shown in Fig. 4, the dark current shows no evident change under V_OFF voltages ranging from −0.4 V to 0 V, while dark current increases sharply for a V_OFF higher than 0 V. For non-irradiated sensor, the dark current slightly increases at V_OFF above 0 V, indicating that the generation of the interface at the TG with 100 krad (SiO₂), the current from the TG is negligible at a V_OFF of 0 V, coming mainly from the STI surrounding the photodiode.

Fig. 4.

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	Fig. 4. (color online) Variation in dark current with VOFF voltage.

The maximum output voltage swing of an image sensor can be limited either by the saturation of the readout circuit or by the full well capacity (FWC) of the PPD.^[12] Therefore, the FWC is one of the main parameters determining the dynamic range of the image sensor. The FWC in the 4T pixel structure is defined as the maximum charge that can be stored in the photodiode capacitor and can be roughly approximated by Q = (V_pin − V_OFF) × C_PPD, where V_pin and C_PPD are the photodiode voltage and capacitance respectively when the photodiode is fully depleted.^[13]

Figure 5 shows that the FWC decays with TID increasing. It is almost impossible to use a sensor to measure the value of the photodiode capacitance without knowing all details of process parameters. There exists an indirect way to measure the change in the photodiode voltage. It relies on the use of the change in the voltage applied to the TG when it is switched off. During the light exposure time, in normal mode, V_OFF is set to be lower than V_pin in order to keep charges in the photodiode. The FWC decreases with the TG voltage V_OFF increasing, and once the value of V_OFF is higher than or equal to V_pin and the TG cannot produce a barrier sufficiently high to prevent charge, no charge will be stored in the photodiode. The schematic diagram of different potential states for different TG voltage situations is shown in Fig. 6.

Fig. 5.

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	Fig. 5. FWC decaying with TID increasing.

Fig. 6.

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	Fig. 6. Schematic diagram of different potential states for different TG voltages.

For the detailed measurement of FWC, V_OFF is swept from 0 V to 2 V, with the integration time and light intensity fixed. The results of this measurement are shown in Fig. 7. The FWC begins to decrease linearly with TG voltage V_OFF increasing gradually in part A, which corresponds to the equation above, Q = (V_pin − V_OFF) × C_PPD. In part B, the FWC does not change with V_OFF increasing. The flat part B is characterized by the TG in a complete “OPEN” state, when the value of V_OFF is higher than or equal to V_pin, and almost no charge in the PD is detected. The value of V_pin can be extracted from the knee-point of the measurement curve, where the PD potential is equal to the TG surface potential. Considering that the TG threshold voltage has no clear degradation, it can be seen in Fig. 7 that there is no significant change in V_pin at 100 krad (SiO₂). Hence, the observed loss in FWC is due to a photodiode capacitance C_PPD after γ ray irradiation. This result can be explained from two aspects. The first one is that the increase in the trap density at the interface leads to the decrease of the doping effective concentration in the pinning layer. The second one is that the radiation induced positive trapped charge could lead to an additional electric field at the interface. Both reasons jointly cause the surface depletion width to extend. Indeed, as in a classical PN-junction, the surface depletion width decreases as the depletion width increases. The PD depletion region expands after irradiation as illustrated by the TCAD simulation shown in Fig. 8.^[14]

Fig. 7.

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	Fig. 7. (color online) Variations of FWC with VOFF for VOFF voltages ranging from 0 V to 2 V before and after irradiation.

Fig. 8.

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	Fig. 8. (color online) PD depletion region expanding after irradiation as illustrated by TCAD simulation.[14]

When the PPD is illuminated by a source of light on the top surface, the absorption of the incoming photons produces photo-electrons, for energy higher than the band gap of silicon. Quantum efficiency (QE) is an important parameter of the image sensor, characterizing the ability to convert photons of a certain wavelength into an effective electrical signal.^[15]

The curve below displays the variations of QE with wavelength for visible spectrum (400 nm–1000 nm), as shown in Fig. 9, before and after γ irradiation. This measurement was performed on the monochromatic sensor without using a micro-lens. One can see that the QE has a clear drop after irradiation at shorter wavelengths, while there is no evidence of changes at longer wavelengths.

Fig. 9.

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	Fig. 9. (color online) Variations of QE with wavelength before and after irradiation.

As shown in Fig. 10, the absorption depth decreases with wavelength decreasing. So, the electrons generated by shorter wavelengths are mainly located near the Si–SiO₂ interface or STI and part of them diffuse into the depletion region. The diffusion length near the interface depends on the recombination lifetime, which corresponds to the Shockley–Read–Hall (SRH) mechanism, owing to the energy levels created by defects.^[16] Hence, the decrease of collection efficiency at shorter wavelengths can be explained by the increase of the interface state density. All this tends to reduce the carrier recombination lifetime near the interface.

Fig. 10.

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	Fig. 10. (color online) Sketch of absorption depth at different wavelengths.

Figure 11 illustrates that the dark currents decrease with annealing time increasing at 100 °C and 200 °C. The dark current recovers about 30% of its post-irradiation value after being annealed at 100 °C for 168 h, and almost disappears during being annealed at 200 °C for 168 h. Most of the interface states encountered in the last decade of CMOS technologies are known to be annealed at high temperature (above 150) while trapped oxide charges are known to disappear after being annealed at 100 °C.^[17] This corresponds to a dark current degradation mechanism where both interface states and trapped oxide charges are responsible for the growing of sensor dark current. It can be found that the annealing of traps induced by irradiation mostly take place at the beginning stage.

Fig. 11.

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	Fig. 11. Variations of dark current with annealing time at different temperatures.