中国物理B ›› 2023, Vol. 32 ›› Issue (1): 18502-018502.doi: 10.1088/1674-1056/ac8f38

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High throughput N-modular redundancy for error correction design of memristive stateful logic

Xi Zhu(朱熙), Hui Xu(徐晖), Weiping Yang(杨为平), Zhiwei Li(李智炜)†, Haijun Liu(刘海军)‡, Sen Liu(刘森), Yinan Wang(王义楠), and Hongchang Long(龙泓昌)   

  1. College of Electronic Science and Technology, National University of Defense Technology, Changsha 410073, China
  • 收稿日期:2022-05-25 修回日期:2022-08-29 接受日期:2022-09-05 出版日期:2022-12-08 发布日期:2023-01-03
  • 通讯作者: Zhiwei Li, Haijun Liu E-mail:lizhiwei@nudt.edu.cn;liuhaijun@nudt.edu.cn
  • 基金资助:
    Project supported by the National Key Research and Development Plan of the Ministry of Science of Technology of China (Grand Nos. 2019YFB 2205100 and 2019YFB 2205102), the National Natural Science Foundation of China (Grant Nos. 61974164, 62074166, 61804181, 62004219, and 62004220), and the Science Support Program of the National University of Defense and Technology (Grand No. ZK20-06).

High throughput N-modular redundancy for error correction design of memristive stateful logic

Xi Zhu(朱熙), Hui Xu(徐晖), Weiping Yang(杨为平), Zhiwei Li(李智炜)†, Haijun Liu(刘海军)‡, Sen Liu(刘森), Yinan Wang(王义楠), and Hongchang Long(龙泓昌)   

  1. College of Electronic Science and Technology, National University of Defense Technology, Changsha 410073, China
  • Received:2022-05-25 Revised:2022-08-29 Accepted:2022-09-05 Online:2022-12-08 Published:2023-01-03
  • Contact: Zhiwei Li, Haijun Liu E-mail:lizhiwei@nudt.edu.cn;liuhaijun@nudt.edu.cn
  • Supported by:
    Project supported by the National Key Research and Development Plan of the Ministry of Science of Technology of China (Grand Nos. 2019YFB 2205100 and 2019YFB 2205102), the National Natural Science Foundation of China (Grant Nos. 61974164, 62074166, 61804181, 62004219, and 62004220), and the Science Support Program of the National University of Defense and Technology (Grand No. ZK20-06).

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摘要： Memristive stateful logic is one of the most promising candidates to implement an in-memory computing system that computes within the storage unit. It can eliminate the costs for the data movement in the traditional von Neumann system. However, the instability in the memristors is inevitable due to the limitation of the current fabrication technology, which incurs a great challenge for the reliability of the memristive stateful logic. In this paper, the implication of device instability on the reliability of the logic event is simulated. The mathematical relationship between logic reliability and redundancy has been deduced. By combining the mathematical relationship with the vector-matrix multiplication in a memristive crossbar array, the logic error correction scheme with high throughput has been proposed. Moreover, a universal design paradigm has been put forward for complex logic. And the circuit schematic and the flow of the scheme have been raised. Finally, a 1-bit full adder (FA) based on the NOR logic and NOT logic is simulated and the mathematical evaluation is performed. It demonstrates the scheme can improve the reliability of the logic significantly. And compared with other four error corrections, the scheme which can be suitable for all kinds of R-R logics and V-R logics has the best universality and throughput. Compared with the other two approaches which also need additional complementary metal-oxide semiconductor (CMOS) circuits, it needs fewer transistors and cycles for the error correction.

关键词: memristor, stateful logic, logic reliability, in-memory computing

Abstract: Memristive stateful logic is one of the most promising candidates to implement an in-memory computing system that computes within the storage unit. It can eliminate the costs for the data movement in the traditional von Neumann system. However, the instability in the memristors is inevitable due to the limitation of the current fabrication technology, which incurs a great challenge for the reliability of the memristive stateful logic. In this paper, the implication of device instability on the reliability of the logic event is simulated. The mathematical relationship between logic reliability and redundancy has been deduced. By combining the mathematical relationship with the vector-matrix multiplication in a memristive crossbar array, the logic error correction scheme with high throughput has been proposed. Moreover, a universal design paradigm has been put forward for complex logic. And the circuit schematic and the flow of the scheme have been raised. Finally, a 1-bit full adder (FA) based on the NOR logic and NOT logic is simulated and the mathematical evaluation is performed. It demonstrates the scheme can improve the reliability of the logic significantly. And compared with other four error corrections, the scheme which can be suitable for all kinds of R-R logics and V-R logics has the best universality and throughput. Compared with the other two approaches which also need additional complementary metal-oxide semiconductor (CMOS) circuits, it needs fewer transistors and cycles for the error correction.

Key words: memristor, stateful logic, logic reliability, in-memory computing

中图分类号:  (Nanoelectronic devices)

  • 85.35.-p
85.25.Hv (Superconducting logic elements and memory devices; microelectronic circuits) 87.85.Qr (Nanotechnologies-design) 84.32.-y (Passive circuit components)