DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

doi:10.1088/1674-1056/ac43a6

中国物理B ›› 2022, Vol. 31 ›› Issue (5): 58501-058501.doi: 10.1088/1674-1056/ac43a6

DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

Zi-Xin Chen(陈子馨)¹, Wei-Jing Liu(刘伟景)^1,†, Jiang-Nan Liu(刘江南)¹, Qiu-Hui Wang(王秋蕙)¹, Xu-Guo Zhang(章徐国)¹, Jie Xu(许洁)¹, Qing-Hua Li(李清华)², Wei Bai(白伟)³, and Xiao-Dong Tang(唐晓东)³

1 College of Electronics and Information Engineering, Shanghai University of Electric Power, Shanghai 200090, China;
2 GTA Semiconductor Corporation Limited, Shanghai 200123, China;
3 Key Laboratory of Polar Materials and Devices, East China Normal University, Shanghai 200041, China

收稿日期:2021-11-01 修回日期:2021-11-27 发布日期:2022-04-21
通讯作者: Wei-Jing Liu,E-mail:liuwj5500@163.com E-mail:liuwj5500@163.com
基金资助:
Project supported by the National Natural Science Foundation of China (Grant Nos.52177185 and 62174055) and Open Fund of Shanghai Key Laboratory of Multidimensional Information Processing,East China Normal University (Grant No.2019MIP002).

DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

1 College of Electronics and Information Engineering, Shanghai University of Electric Power, Shanghai 200090, China;
2 GTA Semiconductor Corporation Limited, Shanghai 200123, China;
3 Key Laboratory of Polar Materials and Devices, East China Normal University, Shanghai 200041, China

Received:2021-11-01 Revised:2021-11-27 Published:2022-04-21
Contact: Wei-Jing Liu,E-mail:liuwj5500@163.com E-mail:liuwj5500@163.com
About author:2021-12-16
Supported by:
Project supported by the National Natural Science Foundation of China (Grant Nos.52177185 and 62174055) and Open Fund of Shanghai Key Laboratory of Multidimensional Information Processing,East China Normal University (Grant No.2019MIP002).

摘要/Abstract

摘要： A C-shaped pocket tunnel field effect transistor (CSP-TFET) has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance. A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability. The effects of the pocket length, pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs. The DC and analog/RF performance such as on-state current (I_on), on/off current ratio (I_on/I_off), subthreshold swing (SS) transconductance (g_m), cut-off frequency (f_T) and gain-bandwidth product (GBP) are investigated. The optimized CSPTFET device exhibits excellent performance with high I_on (9.98×10^{- 4} A/μm), high I_on/I_off (～ 10¹¹), as well as low SS (～ 12 mV/dec). The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.

关键词: tunnel field effect transistor, double gate, pocket

Abstract: A C-shaped pocket tunnel field effect transistor (CSP-TFET) has been designed and optimized based on the traditional double-gate TFETs by introducing a C-shaped pocket region between the source and channel to improve the device performance. A gate-to-pocket overlapping structure is also examined in the proposed CSP-TFET to enhance the gate controllability. The effects of the pocket length, pocket doping concentration and gate-to-pocket overlapping structure on the DC and analog/RF characteristics of the CSP-TFET are estimated after calibrating the tunneling model in double-gate TFETs. The DC and analog/RF performance such as on-state current (I_on), on/off current ratio (I_on/I_off), subthreshold swing (SS) transconductance (g_m), cut-off frequency (f_T) and gain-bandwidth product (GBP) are investigated. The optimized CSPTFET device exhibits excellent performance with high I_on (9.98×10^{- 4} A/μm), high I_on/I_off (～ 10¹¹), as well as low SS (～ 12 mV/dec). The results reveal that the CSP-TFET device could be a potential alternative for the next generation of semiconductor devices.

Key words: tunnel field effect transistor, double gate, pocket

中图分类号: (Junction breakdown and tunneling devices (including resonance tunneling devices))

85.30.Mn

85.30.Tv (Field effect devices) 81.05.Cy (Elemental semiconductors)

Zi-Xin Chen(陈子馨), Wei-Jing Liu(刘伟景), Jiang-Nan Liu(刘江南), Qiu-Hui Wang(王秋蕙), Xu-Guo Zhang(章徐国), Jie Xu(许洁), Qing-Hua Li(李清华), Wei Bai(白伟), and Xiao-Dong Tang(唐晓东). DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate[J]. 中国物理B, 2022, 31(5): 58501-058501.

参考文献

[1] Boucart K and Ionescu A M 2007 IEEE Trans. Electron. Devices 54 1725
[2] Chen Z X, Yu H Y, Singh N, Shen N S, Sayanthan R D, Lo G Q and Kwong D L 2009 IEEE Electron. Device Lett. 30 754
[3] Hu C M, Patel P, Bowonder A, Jeon K, Kim S H, Wei Y L, Chang Y K, Jungwoo O, Majhi P, Javey A, Liu T J K and Jammy R 2010 International Electron Devices Meeting, December 6-8, 2010, San Francisco, CA, USA, p. 16.1.1
[4] Omura Y, Mallik A and Matsuo N 2017 MOS Devices for Low-Voltage and Low-Energy Applications (Singapore: John Wiley & Sons) pp. 53-80
[5] Avci U E, Morris D H and Young I A 2015 IEEE J. Electron. Devices Soc. 3 88
[6] Saurabh S and Kumar M J 2011 IEEE Trans. Electron. Devices 58 404
[7] Lu H and Seabaugh A 2014 IEEE J. Electron. Devices Soc. 2 44
[8] Rajoriya A, Shrivastava M, Gossner H, Schulz T and Rao V R 2013 IEEE Trans. Electron. Devices 60 2626
[9] Ionescu A M and Riel H 2011 Nature 479 329
[10] Yoon Y J, Woo S Y, Seo J H, Lee J S, Park Y S, Lee J H and Kang I M 2012 J. Korean Phys. Soc. 61 1679
[11] Chatterjee N, Gupta A and Pandey S 2016 International Conference on Computational Techniques in Information and Communication Technologies (ICCTICT), March 11-13, 2016, New Delhi, India, p. 118
[12] Kumar N and Raman A 2020 Silicon 12 2627
[13] Kim S W, Kim J H, Liu T J K, Choi W Y and Park B G 2016 IEEE Trans. Electron. Devices 63 1774
[14] Li C, Zhao X L, Zhuang Y Q, Yan Z R, Guo J M and Han R 2018 Superlattices Microstruct. 115 154
[15] Liu K M and Cheng C P 2020 IEEE Trans. Nanotechnol 19 382
[16] Dubey P K, Kaushik B K 2017 IEEE Trans. Electron. Devices 64 3120
[17] Choi W Y and Lee W 2010 IEEE Trans. Electron. Devices 57 2317
[18] Li C, Yan Z R, Zhuang Y Q, Zhao X L and Guo J M 2018 Chin. Phys. B 27 078502
[19] Lee J W and Choi W Y 2020 IEEE Access 8 67617
[20] Avci U E and Young I A 2013 IEEE International Electron Devices Meeting, December 9-11, 2013, Washington, DC, USA, p. 4.3.1
[21] Lu Y Q, Zhou G L, Li R, Liu Q M, Zhang Q, Vasen T, Chae S D, Kosel T, Wistey M, Xing H L, Seabaugh A and Fay P 2012 IEEE Electron. Device Lett. 33 655
[22] Tomioka K, Yoshimura M and Fukui T 2012 Symposium on VLSI Technology (VLSIT), June 12-14 2012, Honolulu, HI, USA, p. 47
[23] Cui N, Liang R R and Xu J 2011 Appl. Phys. Lett. 98 142105
[24] Beneventi G B, Gnani E, Gnudi A, Reggiani S and Baccarani G 2015 IEEE Trans. Electron. Devices 62 44
[25] Seabaugh A C and Zhang Q 2010 Proc. IEEE Inst. Electr. Electron. Eng. 98 2095
[26] Nagavarapu V, Jhaveri R and Woo J C S 2008 IEEE Trans. Electron. Devices 55 1013
[27] Jhaveri R, Nagavarapu V and Woo J C S 2011 IEEE Trans. Electron. Devices 58 80
[28] Li W C and Woo J C S 2018 IEEE Trans. Electron. Devices 65 5289
[29] Kao K H, Verhulst A S, Vandenberghe W G, Soree B, Magnus W, Leonelli D, Groeseneken G and Meyer K De 2012 IEEE Trans. Electron. Devices 59 2070
[30] Abdi D B and Kumar M J 2014 IEEE Electron. Device Lett. 35 1170
[31] Sahoo S, Dash S, Routray S R and Mishra G P 2021 Int. J. Numer. Model. El. 34 e2808
[32] Li W C and Woo J C S 2020 IEEE Trans. Electron. Devices 67 1480
[33] Yang Z N 2016 IEEE Electron. Device Lett. 37 839
[34] Bhuwalka K K, Schulze J and Eisele I 2005 IEEE Trans. Electron. Devices 52 1541
[35] Xie H W and Liu H X 2020 AIP Adv. 10 055125
[36] Dharmender and Nigam K 2020 Silicon 13 2347
[37] Singh A K, Tripathy M R, Baral K, Singh P K and Jit S 2020 Microelectron. J. 102 104775

DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

DC and analog/RF performance of C-shaped pocket TFET (CSP-TFET) with fully overlapping gate

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