中国物理B ›› 2019, Vol. 28 ›› Issue (9): 98502-098502.doi: 10.1088/1674-1056/ab3436
• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇 下一篇
Rui Chen(陈蕊), Dong-Yue Jin(金冬月), Wan-Rong Zhang(张万荣), Li-Fan Wang(王利凡), Bin Guo(郭斌), Hu Chen(陈虎), Ling-Han Yin(殷凌寒), Xiao-Xue Jia(贾晓雪)
Rui Chen(陈蕊), Dong-Yue Jin(金冬月), Wan-Rong Zhang(张万荣), Li-Fan Wang(王利凡), Bin Guo(郭斌), Hu Chen(陈虎), Ling-Han Yin(殷凌寒), Xiao-Xue Jia(贾晓雪)
摘要:
Based on the thermal network of the two-dimensional heterojunction bipolar transistors (HBTs) array, the thermal resistance matrix is presented, including the self-heating thermal resistance and thermal coupling resistance to describe the self-heating and thermal coupling effects, respectively. For HBT cells along the emitter length direction, the thermal coupling resistance is far smaller than the self-heating thermal resistance, and the peak junction temperature is mainly determined by the self-heating thermal resistance. However, the thermal coupling resistance is in the same order with the self-heating thermal resistance for HBT cells along the emitter width direction. Furthermore, the dependence of the thermal resistance matrix on cell spacing along the emitter length direction and cell spacing along the emitter width direction is also investigated, respectively. It is shown that the moderate increase of cell spacings along the emitter length direction and the emitter width direction could effectively lower the self-heating thermal resistance and thermal coupling resistance, and hence the peak junction temperature is decreased, which sheds light on adopting a two-dimensional non-uniform cell spacing layout to improve the uneven temperature distribution. By taking a 2×6 HBTs array for example, a two-dimensional non-uniform cell spacing layout is designed, which can effectively lower the peak junction temperature and reduce the non-uniformity of the dissipated power. For the HBTs array with optimized layout, the high power-handling capability and thermal dissipation capability are kept when the bias voltage increases.
中图分类号: (Semiconductor-device characterization, design, and modeling)