中国物理B ›› 2022, Vol. 31 ›› Issue (9): 97401-097401.doi: 10.1088/1674-1056/ac6743
Cheng-Yu Huang(黄成玉)1, Jin-Yan Wang(王金延)1,†, Bin Zhang(张斌)1, Zhen Fu(付振)2, Fang Liu(刘芳)2, Mao-Jun Wang(王茂俊)1, Meng-Jun Li(李梦军)1, Xin Wang(王鑫)1, Chen Wang(汪晨)1, Jia-Yin He(何佳音)1, and Yan-Dong He(何燕冬)1,‡
Cheng-Yu Huang(黄成玉)1, Jin-Yan Wang(王金延)1,†, Bin Zhang(张斌)1, Zhen Fu(付振)2, Fang Liu(刘芳)2, Mao-Jun Wang(王茂俊)1, Meng-Jun Li(李梦军)1, Xin Wang(王鑫)1, Chen Wang(汪晨)1, Jia-Yin He(何佳音)1, and Yan-Dong He(何燕冬)1,‡
摘要: Based on the self-terminating thermal oxidation-assisted wet etching technique, two kinds of enhancement mode Al$_{2}$O$_{3}$/GaN MOSFETs (metal-oxide-semiconductor field-effect transistors) separately with sapphire substrate and Si substrate are prepared. It is found that the performance of sapphire substrate device is better than that of silicon substrate. Comparing these two devices, the maximum drain current of sapphire substrate device (401 mA/mm) is 1.76 times that of silicon substrate device (228 mA/mm), and the field-effect mobility ($\mu_{\rm FEmax}$) of sapphire substrate device (176 cm$^{2}$/V$\cdot$s) is 1.83 times that of silicon substrate device (96 cm$^{2}$/V$\cdot$s). The conductive resistance of silicon substrate device is 21.2 $\Omega {\cdot }$mm, while that of sapphire substrate device is only 15.2 $\Omega {\cdot }$mm, which is 61% that of silicon substrate device. The significant difference in performance between sapphire substrate and Si substrate is related to the differences in interface and border trap near Al$_{2}$O$_{3}$/GaN interface. Experimental studies show that (i) interface/border trap density in the sapphire substrate device is one order of magnitude lower than in the Si substrate device, (ii) Both the border traps in Al$_{2}$O$_{3}$ dielectric near Al$_{2}$O$_{3}$/GaN and the interface traps in Al$_{2}$O$_{3}$/GaN interface have a significantly effect on device channel mobility, and (iii) the properties of gallium nitride materials on different substrates are different due to wet etching. The research results in this work provide a reference for further optimizing the performances of silicon substrate devices.
中图分类号: (III-V semiconductor-to-semiconductor contacts, p-n junctions, and heterojunctions)