中国物理B ›› 2014, Vol. 23 ›› Issue (2): 28501-028501.doi: 10.1088/1674-1056/23/2/028501
• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇 下一篇
朱玄a b, 唐玉华a b, 吴纯青b, 吴俊杰a b, 易勋a b
Zhu Xuan (朱玄)a b, Tang Yu-Hua (唐玉华)a b, Wu Chun-Qing (吴纯青)b, Wu Jun-Jie (吴俊杰)a b, Yi Xun (易勋)a b
摘要: Nanocrossbar is a potential memory architecture to integrate memristor to achieve large scale and high density memory. However, based on the currently widely-adopted parallel reading scheme, scalability of the nanocrossbar memory is limited, since the overhead of the reading circuits is in proportion with the size of the nanocrossbar component. In this paper, a multiplexed reading scheme is adopted as the foundation of the discussion. Through HSPICE simulation, we reanalyze scalability of the nanocrossbar memristor memory by investigating the impact of various circuit parameters on the output voltage swing as the memory scales to larger size. We find that multiplexed reading maintains sufficient noise margin in large size nanocrossbar memristor memory. In order to improve the scalability of the memory, memristors with nonlinear I–V characteristics and high LRS (low resistive state) resistance should be adopted.
中图分类号: (Computer-aided design of microcircuits; layout and modeling)