中国物理B ›› 2024, Vol. 33 ›› Issue (4): 47302-047302.doi: 10.1088/1674-1056/ad24d7

• • 上一篇    下一篇

Improving the electrical performances of InSe transistors by interface engineering

Tianjun Cao(曹天俊)1, Song Hao(郝松)2,†, Chenchen Wu(吴晨晨)1, Chen Pan(潘晨)2, Yudi Dai(戴玉頔)1, Bin Cheng(程斌)2, Shi-Jun Liang(梁世军)1,‡, and Feng Miao(缪峰)1,§   

  1. 1 Institute of Brain-Inspired Intelligence, National Laboratory of Solid State Microstructures, School of Physics, Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China;
    2 Institute of Interdisciplinary Physical Sciences, School of Physics, Nanjing University of Science and Technology, Nanjing 210014, China
  • 收稿日期:2023-12-12 修回日期:2024-01-30 接受日期:2024-02-01 出版日期:2024-03-19 发布日期:2024-03-22
  • 通讯作者: Song Hao, Shi-Jun Liang, Feng Miao E-mail:hao@nju.edu.cn;sjliang@nju.edu.cn;miao@nju.edu.cn
  • 基金资助:
    Song Hao thanks the support of the National Natural Science Foundation of China (Grant No. 62204030). This work was supported in part by the National Natural Science Foundation of China (Grant Nos. 62122036, 62034004, 61921005, 61974176, and 12074176) and the Strategic Priority Research Program of the Chinese Academy of Sciences (Grant No. XDB44000000)

Improving the electrical performances of InSe transistors by interface engineering

Tianjun Cao(曹天俊)1, Song Hao(郝松)2,†, Chenchen Wu(吴晨晨)1, Chen Pan(潘晨)2, Yudi Dai(戴玉頔)1, Bin Cheng(程斌)2, Shi-Jun Liang(梁世军)1,‡, and Feng Miao(缪峰)1,§   

  1. 1 Institute of Brain-Inspired Intelligence, National Laboratory of Solid State Microstructures, School of Physics, Collaborative Innovation Center of Advanced Microstructures, Nanjing University, Nanjing 210093, China;
    2 Institute of Interdisciplinary Physical Sciences, School of Physics, Nanjing University of Science and Technology, Nanjing 210014, China
  • Received:2023-12-12 Revised:2024-01-30 Accepted:2024-02-01 Online:2024-03-19 Published:2024-03-22
  • Contact: Song Hao, Shi-Jun Liang, Feng Miao E-mail:hao@nju.edu.cn;sjliang@nju.edu.cn;miao@nju.edu.cn
  • Supported by:
    Song Hao thanks the support of the National Natural Science Foundation of China (Grant No. 62204030). This work was supported in part by the National Natural Science Foundation of China (Grant Nos. 62122036, 62034004, 61921005, 61974176, and 12074176) and the Strategic Priority Research Program of the Chinese Academy of Sciences (Grant No. XDB44000000)

RichHTML

0

PDF (PC)

184

赞

补充材料

1

摘要： InSe has emerged as a promising candidate for next-generation electronics due to its predicted ultrahigh electrical performance. However, the efficacy of the InSe transistor in meeting application requirements is hindered due to its sensitivity to interfaces. In this study, we have achieved notable enhancement in the electrical performance of InSe transistors through interface engineering. We engineered an InSe/h-BN heterostructure, effectively suppressing dielectric layer-induced scattering. Additionally, we successfully established excellent metal—semiconductor contacts using graphene ribbons as a buffer layer. Through a methodical approach to interface engineering, our graphene/InSe/h-BN transistor demonstrates impressive on-state current, field-effect mobility, and on/off ratio at room temperature, reaching values as high as 1.1 mA/μm, 904 cm2·V-1·s-1, and >106, respectively. Theoretical computations corroborate that the graphene/InSe heterostructure shows significant interlayer charge transfer and weak interlayer interaction, contributing to the enhanced performance of InSe transistors. This research offers a comprehensive strategy to elevate the electrical performance of InSe transistors, paving the way for their utilization in future electronic applications.

关键词: two-dimensional materials, InSe, van der Waals heterostructure, electrical performances, charge density difference

Abstract: InSe has emerged as a promising candidate for next-generation electronics due to its predicted ultrahigh electrical performance. However, the efficacy of the InSe transistor in meeting application requirements is hindered due to its sensitivity to interfaces. In this study, we have achieved notable enhancement in the electrical performance of InSe transistors through interface engineering. We engineered an InSe/h-BN heterostructure, effectively suppressing dielectric layer-induced scattering. Additionally, we successfully established excellent metal—semiconductor contacts using graphene ribbons as a buffer layer. Through a methodical approach to interface engineering, our graphene/InSe/h-BN transistor demonstrates impressive on-state current, field-effect mobility, and on/off ratio at room temperature, reaching values as high as 1.1 mA/μm, 904 cm2·V-1·s-1, and >106, respectively. Theoretical computations corroborate that the graphene/InSe heterostructure shows significant interlayer charge transfer and weak interlayer interaction, contributing to the enhanced performance of InSe transistors. This research offers a comprehensive strategy to elevate the electrical performance of InSe transistors, paving the way for their utilization in future electronic applications.

Key words: two-dimensional materials, InSe, van der Waals heterostructure, electrical performances, charge density difference

中图分类号:  (Electron states at surfaces and interfaces)

  • 73.20.-r
73.40.Ns (Metal-nonmetal contacts)