中国物理B ›› 2013, Vol. 22 ›› Issue (11): 117309-117309.doi: 10.1088/1674-1056/22/11/117309

• CONDENSED MATTER: ELECTRONIC STRUCTURE, ELECTRICAL, MAGNETIC, AND OPTICAL PROPERTIES • 上一篇    下一篇

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

许高博, 徐秋霞, 殷华湘, 周华杰, 杨涛, 牛洁斌, 余嘉晗, 李俊峰, 赵超   

  1. Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
  • 收稿日期:2013-03-07 修回日期:2013-06-20 出版日期:2013-09-28 发布日期:2013-09-28
  • 基金资助:
    Project supported by the Beijing Natural Science Foundation, China (Grant No. 4123106) and the National Science and Technology Major Projects of the Ministry of Science and Technology of China (Grant No. 2009ZX02035).

A high performance HfSiON/TaN NMOSFET fabricated using a gate-last process

Xu Gao-Bo (许高博), Xu Qiu-Xia (徐秋霞), Yin Hua-Xiang (殷华湘), Zhou Hua-Jie (周华杰), Yang Tao (杨涛), Niu Jie-Bin (牛洁斌), Yu Jia-Han (余嘉晗), Li Jun-Feng (李俊峰), Zhao Chao (赵超)   

  1. Key Laboratory of Microelectronics Devices & Integrated Technology, Institute of Microelectronics, Chinese Academy of Sciences, Beijing 100029, China
  • Received:2013-03-07 Revised:2013-06-20 Online:2013-09-28 Published:2013-09-28
  • Contact: Xu Gao-Bo E-mail:xugaobo@ime.ac.cn
  • Supported by:
    Project supported by the Beijing Natural Science Foundation, China (Grant No. 4123106) and the National Science and Technology Major Projects of the Ministry of Science and Technology of China (Grant No. 2009ZX02035).

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摘要： A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 Å was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide (TMAH) wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device’s gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μ. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage (～ 0.24 V) for high performance NMOSFETs. The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.

关键词: HfSiON, TaN, gate-last process, planarization

Abstract: A gate-last process for fabricating HfSiON/TaN n-channel metal-oxide-semiconductor-field-effect transistors (NMOSFETs) is presented. In the process, a HfSiON gate dielectric with an equivalent oxide thickness of 10 Å was prepared by a simple physical vapor deposition method. Poly-Si was deposited on the HfSiON gate dielectric as a dummy gate. After the source/drain formation, the poly-Si dummy gate was removed by tetramethylammonium hydroxide (TMAH) wet-etching and replaced by a TaN metal gate. Because the metal gate was formed after the ion-implant doping activation process, the effects of the high temperature process on the metal gate were avoided. The fabricated device exhibits good electrical characteristics, including good driving ability and excellent sub-threshold characteristics. The device’s gate length is 73 nm, the driving current is 117 μA/μm under power supply voltages of VGS=VDS=1.5 V and the off-state current is only 4.4 nA/μ. The lower effective work function of TaN on HfSiON gives the device a suitable threshold voltage (～ 0.24 V) for high performance NMOSFETs. The device’s excellent performance indicates that this novel gate-last process is practical for fabricating high performance MOSFETs.

Key words: HfSiON, TaN, gate-last process, planarization

中图分类号:  (Metal-insulator-semiconductor structures (including semiconductor-to-insulator))

  • 73.40.Qv
73.61.-r (Electrical properties of specific thin films) 73.90.+f (Other topics in electronic structure and electrical properties of surfaces, interfaces, thin films, and low-dimensional structures)