中国物理B ›› 2012, Vol. 21 ›› Issue (8): 84210-084210.doi: 10.1088/1674-1056/21/8/084210

• ELECTROMAGNETISM, OPTICS, ACOUSTICS, HEAT TRANSFER, CLASSICAL MECHANICS, AND FLUID DYNAMICS • 上一篇    下一篇

Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable Gm–C loop filter

黄进芳a, 刘荣宜b, 赖文政a, 石钧纬a, 许剑铭a   

  1. a Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 10672, Taiwan, China;
    b Chunghwa Telecommunication Laboratory, Chunghwa Telecom. Co., Taoyuan 32617, Taiwan, China
  • 收稿日期:2011-07-10 修回日期:2011-08-11 出版日期:2012-07-01 发布日期:2012-07-01

Chip design of a 5.8-GHz fractional-N frequency synthesizer with a tunable Gm–C loop filter

Huang Jhin-Fang (黄进芳)a, Liu Ron-Yi (刘荣宜)b, Lai Wen-Cheng (赖文政)a, Shin Chun-Wei (石钧纬)a, Hsu Chien-Ming (许剑铭 )a   

  1. a Department of Electronic Engineering, National Taiwan University of Science and Technology, Taipei 10672, Taiwan, China;
    b Chunghwa Telecommunication Laboratory, Chunghwa Telecom. Co., Taoyuan 32617, Taiwan, China
  • Received:2011-07-10 Revised:2011-08-11 Online:2012-07-01 Published:2012-07-01
  • Contact: Lai Wen-Cheng E-mail:eway1217@gmail.com

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摘要： This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore the MASH 1-1-1 sigma-delta (Σ Δ) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and build-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 GHz and consumes 56 mW with off-chip buffer from 1.8-V supply voltage.

关键词: Gm-C loop filter, phase-locked loop, PLL, voltage-controlled oscillator (VCO)

Abstract: This paper proposes a novel Gm-C loop filter instead of a conventional passive loop filter used in phase-locked loop. The innovative advantage of the proposed architecture is tunable loop filter bandwidth and hence the process variations of passive elements of resistance R and capacitance C can be overcome and the chip area is greatly reduced. Furthermore the MASH 1-1-1 sigma-delta (Σ Δ) modulator is adopted for performing the fractional division number and hence improves the phase noise as well. Measured results show that the locked phase noise is -114.1 dBc/Hz with lower Gm-C bandwidth and -111.7 dBm/C with higher Gm-C bandwidth at 1 MHz offset from carrier of 5.68 GHz. Including pads and build-in Gm-C filter, the chip area of the proposed frequency synthesizer is 1.06 mm2. The output power is -8.69 dBm at 5.68 GHz and consumes 56 mW with off-chip buffer from 1.8-V supply voltage.

Key words: Gm-C loop filter, phase-locked loop, PLL, voltage-controlled oscillator (VCO)

中图分类号: 

  • 42.62.Fh
42.79.Ci (Filters, zone plates, and polarizers)