Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit

doi:10.1088/1674-1056/23/3/038401

中国物理B ›› 2014, Vol. 23 ›› Issue (3): 38401-038401.doi: 10.1088/1674-1056/23/3/038401

• INTERDISCIPLINARY PHYSICS AND RELATED AREAS OF SCIENCE AND TECHNOLOGY • 上一篇下一篇

Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit

刘晓贤, 朱樟明, 杨银堂, 王凤娟, 丁瑞雪

Microelectronics School, Xidian University, Xi’an 710071, China

收稿日期:2013-05-21 修回日期:2013-07-18 出版日期:2014-03-15 发布日期:2014-03-15
基金资助:
Project supported by the National Natural Science Foundation of China (Grant No. 61204044).

Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit

Liu Xiao-Xian (刘晓贤), Zhu Zhang-Ming (朱樟明), Yang Yin-Tang (杨银堂), Wang Feng-Juan (王凤娟), Ding Rui-Xue (丁瑞雪)

Microelectronics School, Xidian University, Xi’an 710071, China

Received:2013-05-21 Revised:2013-07-18 Online:2014-03-15 Published:2014-03-15
Contact: Liu Xiao-Xian E-mail:liudou132@163.com
Supported by:
Project supported by the National Natural Science Foundation of China (Grant No. 61204044).

摘要/Abstract

摘要： The through silicon via (TSV) technology has proven to be the critical enabler to realize a three-dimensional (3D) gigscale system with higher performance but shorter interconnect length. However, the received digital signal after transmission through a TSV channel, composed of redistribution layers (RDLs), TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflection of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient (S₁₁) and signal transmission coefficient (S₂₁) are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance (RLGC) elements of the TSV channel are iterated from scattering (S)-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure (HFSS) simulation software by Ansoft.

关键词: three-dimensional integrated circuit, through silicon via channel, signal reflection, S-parameters

Abstract: The through silicon via (TSV) technology has proven to be the critical enabler to realize a three-dimensional (3D) gigscale system with higher performance but shorter interconnect length. However, the received digital signal after transmission through a TSV channel, composed of redistribution layers (RDLs), TSVs, and bumps, is degraded at a high data-rate due to the non-idealities of the channel. We propose the Chebyshev multisection transformers to reduce the signal reflection of TSV channel when operating frequency goes up to 20 GHz, by which signal reflection coefficient (S₁₁) and signal transmission coefficient (S₂₁) are improved remarkably by 150% and 73.3%, respectively. Both the time delay and power dissipation are also reduced by 4% and 13.3%, respectively. The resistance-inductance-conductance-capacitance (RLGC) elements of the TSV channel are iterated from scattering (S)-parameters, and the proposed method of weakening the signal reflection is verified using high frequency simulator structure (HFSS) simulation software by Ansoft.

Key words: three-dimensional integrated circuit, through silicon via channel, signal reflection, S-parameters

中图分类号: (Electronic circuits)

84.30.-r

84.30.Bv (Circuit theory)

刘晓贤, 朱樟明, 杨银堂, 王凤娟, 丁瑞雪. Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit[J]. 中国物理B, 2014, 23(3): 38401-038401.

Liu Xiao-Xian (刘晓贤), Zhu Zhang-Ming (朱樟明), Yang Yin-Tang (杨银堂), Wang Feng-Juan (王凤娟), Ding Rui-Xue (丁瑞雪). Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit[J]. Chin. Phys. B, 2014, 23(3): 38401-038401.

参考文献 17

[1]	Kim J, Pak J S, Cho J H, Song E, Cho J, Kim H, Song T, Lee J, Lee H, Park K, Yang S, Suh M S, Byun K Y and Kim J H 2011 IEEE Trans. Compon. Pack. Manuf. Technol. 1 181
[2]	Katti G, Michele S, Velenis D, Thangaraju S, Meyer K, Dehaene W and Beyne E 2011 IEEE Electron Dev. Lett. 32 946
[3]	Kim H, Cho J, Kim M, Kim K, Lee J, Lee H, Park K, Choi K, Bae H C, Kim H J and Kim J 2012 IEEE Trans. Compon. Pack. Manuf. Technol. 2 1672
[4]	Zhu Z M and Liu S B 2012 Chin. Phys. B 21 028401
[5]	Zhang Y, Dong G and Yang Y T 2013 Acta Phys. Sin. 62 016601 (in Chinese)
[6]	Yu Y, Zhang C and Han X J 2013 Acta Phys. Sin. 62 020508 (in Chinese)
[7]	Qian L B, Zhu Z M and Yang Y T 2011 Chin. Phys. B 20 108401
[8]	Lee M, Cho J, Kim J, Pak J S, Lee H, Lee J, Park K and Kim J H 2012 Proceedings of 62th Electronic Components and Technology Conference (ECTC), May 29–June 1, 2012, San Diego, America, p. 816
[9]	Cui Q H, Sun X, Zhu Y H, Ma S L, Chen J, Miao M and Jin Y F 2011 Proceeding of 12th Electronic Packaging Technology & High Density Packaging, August 8–11, 2011, Shanghai, China, p. 1
[10]	Hu S, Wang L, Xiong Y Z, Lim T G, Zhang B, Shi J L and Yuan X J 2011 IEEE Trans. Compon. Pack. Manuf. Technol. 1 260
[11]	Xu Z and Lu J Q 2011 IEEE Electron Dev. Lett. 32 1278
[12]	Lu K C, Horng T S, Li H H, Fan K C, Huang T Y and Lin C H 2012 Proceedings of 62th Electronic Components and Technology Conference (ECTC), May 29–June 1, 2012, San Diego, America, p. 816
[13]	Wang R, Charles G and Franzon P 2012 Proceedings of 3D Systems Integration Conference (3DIC), January 31–Febrary 2, 2012, Osaka, Japan, p. 1
[14]	Lim T G, Khoo Y M, Selvanayagam C S, Ho D S W, Li R, Zhang X W, Gao S and Yong X Z 2011 Proceedings of 61th Electronic Components and Technology Conference (ECTC), May 32–June 3, 2011, Lake Buena Vista, America, p. 557
[15]	David M P 2012 Microwave Engineering (4th edn.) (New York: John Wiley & Sons) pp. 256–259
[16]	Hall S H, Hall G W and Call J 2000 High-Speed Digital System Design: A Handbook of Interconnect Theory and Design Practices (New York: John Wiley& Sons)
[17]	Davis J A and Meindl J D 2003 Interconnect Technology and Design for Gig Scale Integration (Netherlands: Springer) p. 184

Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit

Reduction of signal reflection along through silicon via channel in high-speed three-dimensional integration circuit

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