Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits

doi:10.1088/1674-1056/ac70b9

中国物理B ›› 2022, Vol. 31 ›› Issue (9): 98501-098501.doi: 10.1088/1674-1056/ac70b9

Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits

Ruo-Ting Yang(杨若婷)^1,2,3, Xin-Yi Xue(薛新伊)⁴, Shu-Cheng Yang(杨树澄)^1,2, Xiao-Ping Gao(高小平)^1,2, Jie Ren(任洁)^1,2,3,†, Wei Yan(严伟)^4,‡, and Zhen Wang(王镇)^1,2,3

1 State Key Laboratory of Functional Material for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China;
2 CAS Center for Excellence in Superconducting Electronics(CENSE), Shanghai 200050, China;
3 University of Chinese Academy of Sciences, Beijing 100049, China;
4 School of Software and Microelectronics, Peking University, Beijing 100871, China

收稿日期:2022-01-26 修回日期:2022-05-13 接受日期:2022-05-18 出版日期:2022-08-19 发布日期:2022-08-19
通讯作者: Jie Ren, Wei Yan E-mail:jieren@mail.sim.ac.cn;yanwei@ss.pku.edu.cn
基金资助:
This work was supported by the National Natural Science Foundation of China (Grant No. 92164101), the National Natural Science Foundation of China (Grant No. 62171437), the Strategic Priority Research Program of the Chinese Academy of Sciences (Grant No. XDA18000000), Shanghai Science and Technology Committee (Grant No. 21DZ1101000), and the National Key R&D Program of China (Grant No. 2021YFB0300400). The authors would like to thank YaJun Ha, Bin-Han Liu and Ling Xin for the valuable discussion and help. The fabrication was performed in the Superconducting Electronics Facility (SELF) of SIMIT.

Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits

Ruo-Ting Yang(杨若婷)^1,2,3, Xin-Yi Xue(薛新伊)⁴, Shu-Cheng Yang(杨树澄)^1,2, Xiao-Ping Gao(高小平)^1,2, Jie Ren(任洁)^1,2,3,†, Wei Yan(严伟)^4,‡, and Zhen Wang(王镇)^1,2,3

1 State Key Laboratory of Functional Material for Informatics, Shanghai Institute of Microsystem and Information Technology, Chinese Academy of Sciences, Shanghai 200050, China;
2 CAS Center for Excellence in Superconducting Electronics(CENSE), Shanghai 200050, China;
3 University of Chinese Academy of Sciences, Beijing 100049, China;
4 School of Software and Microelectronics, Peking University, Beijing 100871, China

Received:2022-01-26 Revised:2022-05-13 Accepted:2022-05-18 Online:2022-08-19 Published:2022-08-19
Contact: Jie Ren, Wei Yan E-mail:jieren@mail.sim.ac.cn;yanwei@ss.pku.edu.cn
Supported by:
This work was supported by the National Natural Science Foundation of China (Grant No. 92164101), the National Natural Science Foundation of China (Grant No. 62171437), the Strategic Priority Research Program of the Chinese Academy of Sciences (Grant No. XDA18000000), Shanghai Science and Technology Committee (Grant No. 21DZ1101000), and the National Key R&D Program of China (Grant No. 2021YFB0300400). The authors would like to thank YaJun Ha, Bin-Han Liu and Ling Xin for the valuable discussion and help. The fabrication was performed in the Superconducting Electronics Facility (SELF) of SIMIT.

摘要/Abstract

摘要： Rapid single flux quantum (RSFQ) circuits are a kind of superconducting digital circuits, having properties of a natural gate-level pipelining synchronous sequential circuit, which demonstrates high energy efficiency and high throughput advantage. We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm, whereas these are rarely applied to this field. Among the available encryption algorithms, the advanced encryption standard (AES) algorithm is an advanced encryption standard algorithm. It is currently the most widely used symmetric cryptography algorithm. In this work, we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb03 process. We design an AES S-bbox circuit in the RSFQ logic, and compare its operational frequency, power dissipation, and throughput with those of the CMOS-based circuit post-simulated in the same structure. The complete RSFQ S-bbox circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz. Our analysis shows that the frequency and throughput of the RSFQ-based S-bbox are about four times higher than those of the CMOS-based S-bbox. Further, we design and fabricate a few typical modules of the S-box. Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.

关键词: RSFQ, AES, S-box, hardware implementation

Abstract: Rapid single flux quantum (RSFQ) circuits are a kind of superconducting digital circuits, having properties of a natural gate-level pipelining synchronous sequential circuit, which demonstrates high energy efficiency and high throughput advantage. We find that the high-throughput and high-speed performance of RSFQ circuits can take the advantage of a hardware implementation of the encryption algorithm, whereas these are rarely applied to this field. Among the available encryption algorithms, the advanced encryption standard (AES) algorithm is an advanced encryption standard algorithm. It is currently the most widely used symmetric cryptography algorithm. In this work, we aim to demonstrate the SubByte operation of an AES-128 algorithm using RSFQ circuits based on the SIMIT Nb03 process. We design an AES S-bbox circuit in the RSFQ logic, and compare its operational frequency, power dissipation, and throughput with those of the CMOS-based circuit post-simulated in the same structure. The complete RSFQ S-bbox circuit costs a total of 42237 Josephson junctions with nearly 130 Gbps throughput under the maximum simulated frequency of 16.28 GHz. Our analysis shows that the frequency and throughput of the RSFQ-based S-bbox are about four times higher than those of the CMOS-based S-bbox. Further, we design and fabricate a few typical modules of the S-box. Subsequent measurements demonstrate the correct functioning of the modules in both low and high frequencies up to 28.8 GHz.

Key words: RSFQ, AES, S-box, hardware implementation

中图分类号: (Superconducting devices)

85.25.-j

85.25.Cp (Josephson devices) 85.25.Hv (Superconducting logic elements and memory devices; microelectronic circuits)

Ruo-Ting Yang(杨若婷), Xin-Yi Xue(薛新伊), Shu-Cheng Yang(杨树澄), Xiao-Ping Gao(高小平), Jie Ren(任洁), Wei Yan(严伟), and Zhen Wang(王镇). Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits[J]. 中国物理B, 2022, 31(9): 98501-098501.

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Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits

Implementation of an 8-bit bit-slice AES S-box with rapid single flux quantum circuits

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