中国物理B ›› 2006, Vol. 15 ›› Issue (1): 195-198.doi: 10.1088/1009-1963/15/1/031

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Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

孙宝刚1, 马晓华2, 郝跃2, 高海霞2, 任红霞2, 张进城2, 张金凤2, 张晓菊2, 张卫东3   

  1. (1)Microelectronics Institute, Chinese Academy of Sciences, Beijing 100029, China; (2)Microelectronics Institute, Xidian University, Xi'an 710071, China;Key Laboratory of Ministry of Education for Wide Band-gap Semiconductor Materials and Devices,Xidian University, Xi'an 710071, China; (3)School of Design, Engineering and Computing, Bournemouth University, UK
  • 收稿日期:2005-03-29 修回日期:2005-09-09 出版日期:2006-01-20 发布日期:2006-01-20
  • 基金资助:
    Project supported by the National Natural Science Foundation of China (Grant No 60376024).

Fabrication and characterization of groove-gate MOSFETs based on a self-aligned CMOS process

Ma Xiao-Hua (马晓华)ab, Hao Yue (郝跃)ab, Sun Bao-Gang (孙宝刚)c, Gao Hai-Xia (高海霞)ab, Ren Hong-Xia (任红霞)ab, Zhang Jin-Cheng (张进城)ab, Zhang Jin-Feng (张金凤)ab, Zhang Xiao-Ju (张晓菊)ab, Zhang Wei-Dong (张卫东)d   

  1. a Microelectronics Institute, Xidian University, Xi'an 710071, China; b Key Laboratory of Ministry of Education for Wide Band-gap Semiconductor Materials and Devices,Xidian University, Xi'an 710071, Chinac Microelectronics Institute, Chinese Academy of Sciences, Beijing 100029, China; d School of Design, Engineering and Computing, Bournemouth University, UK
  • Received:2005-03-29 Revised:2005-09-09 Online:2006-01-20 Published:2006-01-20
  • Supported by:
    Project supported by the National Natural Science Foundation of China (Grant No 60376024).

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摘要： N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.

关键词: self-aligned, groove-gate MOSFETs, DIBL, short-channeleffects

Abstract: N and P-channel groove-gate MOSFETs based on a self-aligned CMOS process have been fabricated and characterized. For the devices with channel length of 140nm, the measured drain induced barrier lowering (DIBL) was 66mV/V for n-MOSFETs and 82mV/V for p-MOSFETs. The substrate current of a groove-gate n-MOSFET was 150 times less than that of a conventional planar n-MOSFET. These results demonstrate that groove-gate MOSFETs have excellent capabilities in suppressing short-channel effects. It is worth emphasizing that our groove-gate MOSFET devices are fabricated by using a simple process flow, with the potential of fabricating devices in the sub-100nm range.

Key words: self-aligned, groove-gate MOSFETs, DIBL, short-channeleffects

中图分类号:  (Field effect devices)

  • 85.30.Tv
85.30.De (Semiconductor-device characterization, design, and modeling) 85.40.-e (Microelectronics: LSI, VLSI, ULSI; integrated circuit fabrication technology)