Asymmetric charge trapping and emission kinetics in SiO₂/HfO₂ for accurate transistor reliability simulation

Charge trapping in gate dielectrics governs reliability degradation in advanced transistors, and an essential mission is calculating the trapping rates of different defects accurately. Here, by high-throughput ab initio calculations, we demonstrate a significant asymmetric relaxation behavior of oxide defects during charge trapping and emission, and thus the predominantly assumed symmetric relaxation is invalid. Multiscale atomic-to-device simulations further reveal that the conventional symmetric approximation introduces orders-of-magnitude errors in charge transfer rates and qualitatively mischaracterizes the defect-resolved degradation. Therefore, we provide asymmetric relaxation data and corresponding modified charge trapping model for accurate reliability simulation of advanced transistors.