Impact of symmetric gate-recess length on the DC and RF characteristics of InP HEMTs

We fabricated a set of symmetric gate-recess devices with gate length of 70nm. We kept the source-to-drain spacing (L_SD) unchanged, and obtained a group of devices with gate-recess length (L_recess) from 0.4\mum to 0.8\mum through process improvement. In order to suppress the influence of the kink effect, we have done SiN_X passivation treatment. The maximum saturation current density (I_D\_max) and maximum transconductance (g_m,max) increase as L_recess decreases to 0.4\mum. At this time, the device shows I_D\_max=749.6mA/mm at V_GS=0.2V, V_DS=1.5V, and g_m\_max=1111mS/mm at V_GS=-0.35V, V_DS=1.5V. Meanwhile, as L_recess increases, it causes parasitic capacitance C_gd and g_d to decrease, making f_max drastically increases. When L_recess=0.8\mum, the device shows f_T=188GHz and f_max=1112GHz.