Dark count rate and band to band tunneling optimization for single photon avalanche diode topologies

This paper proposes two optimal designs of single photon avalanche diodes (SPADs) minimizing dark count rate (DCR). The first structure is introduced as p⁺/pwell/nwell, in which a specific shallow pwell layer is added between p⁺ and nwell layers to decrease the electric field below a certain threshold. The simulation results show on average 19.7% and 8.5% reduction of p⁺/nwell structure's DCR comparing with similar previous structures in different operational excess bias and temperatures respectively. Moreover, a new structure is introduced as n⁺/nwell/pwell, in which a specific shallow nwell layer is added between n⁺ and pwell layers to lower the electric field below a certain threshold. The simulation results show on average 29.2% and 5.5% decrement of p⁺/nwell structure's DCR comparing with similar previous structures in different operational excess bias and temperatures respectively. It is shown that in higher excess biases (about 6 volts), the n⁺/nwell/pwell structure is proper to be integrated as digital silicon photomultiplier (dSiPM) due to low DCR. On the other hand, the p⁺/pwell/nwell structure is appropriate to be utilized in dSiPM in high temperatures (above 50 ℃) due to lower DCR value.