Two-dimensional floating-gate transistors with sub-10 nm MoS₂ channel for artificial synapses

High-density integration of synaptic transistors is crucial for the development of neuromorphic computing. However, aggressively scaling conventional silicon-based floating-gate devices to the sub-10 nm regime is hindered by severe short-channel effects. Here, we report two-dimensional floating-gate artificial synapses based on monolayer MoS_2 with channel lengths scaled down to the sub-10 nm limit. By integrating a high-\kappa hybrid Y_2O_3/HfO_2 dielectric layer, the sub-10 nm transistor achieves excellent electrostatic control, yielding an ultra-high on/off ratio exceeding 10^9. The sub-10 nm channel devices exhibit robust non-volatile memory performance, featuring a data retention exceeding 10^5 s and an endurance of over 5500 cycles. Furthermore, the sub-10 nm channel memory can work as an artificial synapse and demonstrates highly linear weight updates across 64 distinct conductance states with nonlinearity of \sim 0.50 for potentiation and \sim 0.13 for depression. Implementing these experimental characteristics into a VGG-11 convolutional neural network yields a high image recognition accuracy of \sim 93.35% on the CIFAR-10 dataset. Our work demonstrates that ultra-scaled 2D floating-gate transistors offer a viable and highly robust platform for future high-density, energy-efficient neuromorphic hardware.