Low switching loss and increased short-circuit capability split-gate SiC trench MOSFET with p-type pillar

A split-gate SiC trench gate MOSFET with stepped thick oxide, source-connected split-gate (SG), and p-type pillar (p-pillar) surrounded thick oxide shielding region (GSDP-TMOS) is investigated by Silvaco TCAD simulations. The source-connected SG region and p-pillar shielding region are introduced to form an effective two-level shielding, which reduces the specific gate–drain charge ( Q _gd,sp) and the saturation current, thus reducing the switching loss and increasing the short-circuit capability. The thick oxide that surrounds a p-pillar shielding region efficiently protects gate oxide from being damaged by peaked electric field, thereby increasing the breakdown voltage ( BV). Additionally, because of the high concentration in the n-type drift region, the electrons diffuse rapidly and the specific on-resistance ( R _on,sp) becomes smaller. In the end, comparing with the bottom p ⁺ shielded trench MOSFET (GP-TMOS), the Baliga figure of merit (BFOM, BV ²/ R _on,sp) is increased by 169.6%, and the high-frequency figure of merit (HF-FOM, R _on,sp × Q _gd,sp) is improved by 310%, respectively.