Near-interface oxide traps in 4H-SiC MOS structures fabricated with and without annealing in NO

Near-interface oxide traps (NIOTs) in 4H-SiC metal-oxide-semiconductor (MOS) structures fabricated with and without annealing in NO are systematically investigated in this paper. The properties of NIOTs in SiC MOS structures prepared with and without annealing in NO are studied and compared in detail. Two main categories of the NIOTs, the “slow” and “fast” NIOTs, are revealed and extracted. The densities of the “fast” NIOTs are determined to be 0.76×10¹¹ cm^-2 and 0.47×10¹¹ cm^-2 for the N₂ post oxidation annealing (POA) sample and NO POA sample, respectively. The densities of “slow” NIOTs are 0.79×10¹¹ cm^-2 and 9.44×10¹¹ cm^-2 for the NO POA sample and N₂ POA sample, respectively. It is found that the NO POA process only can significantly reduce “slow” NIOTs. However, it has a little effect on “fast” NIOTs. The negative and positive constant voltage stresses (CVS) reveal that electrons captured by those “slow” NIOTs and bulk oxide traps (BOTs) are hardly emitted by the constant voltage stress.