Detailed study of NBTI characterization in 40-nm CMOS process using comprehensive models

The impact of negative bias temperature instability (NBTI) can be ascribed to three mutually uncorrelated factors, including hole trapping by pre-existing traps (△ V_HT) in gate insulator, generated traps (△ V_OT) in bulk insulator, and interface trap generation (△ V_IT). In this paper, we have experimentally investigated the NBTI characteristic for a 40-nm complementary metal-oxide semiconductor (CMOS) process. The power-law time dependence, temperature activation, and field acceleration have also been explored based on the physical reaction-diffusion model. Moreover, the end-of-life of stressed device dependent on the variation of stress field and temperature have been evaluated. With the consideration of locking effect, the recovery characteristics have been modelled and discussed.