Temperature- and voltage-dependent trap generation model in high-k metal gate MOS device with percolation simulation

High-k metal gate stacks are being used to suppress the gate leakage due to tunneling for sub-45 nm technology nodes. The reliability of thin dielectric films becomes a limitation to device manufacturing, especially to the breakdown characteristic. In this work, a breakdown simulator based on a percolation model and the kinetic Monte Carlo method is set up, and the intrinsic relation between time to breakdown and trap generation rate R is studied by TDDB simulation. It is found that all degradation factors, such as trap generation rate time exponent m, Weibull slope β and percolation factor s, each could be expressed as a function of trap density time exponent α. Based on the percolation relation and power law lifetime projection, a temperature related trap generation model is proposed. The validity of this model is confirmed by comparing with experiment results. For other device and material conditions, the percolation relation provides a new way to study the relationship between trap generation and lifetime projection.