Effect of STI-induced mechanical stress on leakage current in deep submicron CMOS devices

The shallow trench isolation (STI) induced mechanical stress significantly affects the CMOS device off-state leakage behaviour. In this paper, we designed two types of devices to investigate this effect, and all leakage components, including sub-threshold leakage (I_\rm sub), gate-induced-drain-leakage (I_\rm GIDL), gate edge-direct-tunnelling leakage (I_\rm EDT) and band-to-band-tunnelling leakage (I_\rm BTBT) were analysed. For NMOS, I_\rm sub can be reduced due to the mechanical stress induced higher boron concentration in well region. However, the GIDL component increases simultaneously as a result of the high well concentration induced drain-to-well depletion layer narrowing as well as the shrinkage of the energy gap. For PMOS, the only mechanical stress effect on leakage current is the energy gap narrowing induced GIDL increase.