Binary digital computing based on memory technologies. (a) Schematic of the classification accelerator constructed by carbon nanotubes field-effect transistors. Left: a monolithic 3D cell for the three-dimensional integration nanosystem. Right: component diagram of the CNFET computational layer. (b) In situ memory logic in a 2D vertical dual-gate transistor. Left: schematic of the 2D vertical dual-gate transistor structure. Right: demonstration of the logic behavior in the 2D vertical dual-gate transistor with a floating gate. (c) Stateful logic enabled by resistive switch devices. Upper: basic material implication (IMP) logic implementation. Bottom: NAND logic implementation method based on IMP and FALSE logic. (d) Full adder based on stateful logic computing of resistive switches. Left: circuit diagram and the corresponding equivalent networks of a full adder. Right: the truth table of the full adder logic. Panel (a) is reproduced from Ref. [37]. Panel (c) is reproduced from Ref. [50]. Panel (d) is reproduced from Ref. [21].