Stochastic applications based on memory technologies. (a) Top view of an RRAM PUF chip with the key parameters and cell layout. (b) Comparison of performance between the RRAM PUF and other technologies for PUF. (c) Schematic of generating random numbers with the delay time from the memory devices. (d) Diagram of using one AND gate to complete fractional multiplication with generated random number streams. (e) Factorization using stochastic magnetic tunnel junctions. Left: printed circuit board of the interconnected MTJ circuit. Right: electrical schematic of a stochastic MTJ with external circuit components. Panel (a) is reproduced from Ref. [130]. Panel (c) inset is reproduced from Ref. [16]. Panel (e) inset is reproduced from Ref. [138].