Neural network demonstrations on the crossbar array. (a) Schematic diagram of a simple neural network. (b) Hardware implementation of neural network in an RRAM crossbar array. (c) A fully integrated chip with a 54 × 108 crossbar array fabricated on a CMOS substrate. (d) Schematic of the interface to the 54 × 108 crossbar array, with three read/write DACs and one ADC for each row and column. (e) The mapping of a bilayer network consisted of a 9 × 2 subarray for the PCA layer and a 3 × 2 subarray for the classification layer in the 54 × 108 crossbar array. (f) Schematic of a five-layer memristor-based CNN used for MNIST image recognition with eight 2048-cell memristor arrays. Panels (c), (d), and (e) are reproduced from Ref. [23]. Panel (f) inset is reproduced from Ref. [24].