High-performance synaptic transistors for neuromorphic computing

Zhong Hai¹, Sun Qin-Chao¹, Li Guo¹, Du Jian-Yu^{1, 2}, Huang He-Yi^{1, 2}, Guo Er-Jia^{1, 3}, He Meng¹, Wang Can^{1, 2, 4}, Yang Guo-Zhen¹, Ge Chen^{1, 2, †}, Jin Kui-Juan^{1, 2, 4, ‡}

(a) Schematic of fabricated FGT with upward polarization and downward. (b) Change of the drain current before and after applying the pulsed gate voltage with various heights and widths. Reprinted with permission from Ref. [38]. Copyright 2012, AIP Publishing. (c) Illustration of suggested mechanism of multi-level data storage. (d) Potentiation and depression properties of ferroelectric thin-film transistor with incremental pulse scheme. Reprinted with permission from Ref. [90]. Copyright 2019, American Chemical Society.