(a) The “write” and (b) “read” states of an IFG cell consisting of a CBM and a redox transistor. (c) Programming of an IFG cell at two different write voltages. (d) Schematic of a 1-by-2 IFG resistive memory array. (e) Selective addressing by subjecting G₁₁ or G₁₂ to 50 weight updates without disturbing the adjacent element. (f) Demonstration of > 10⁸ write–read operations without deterioration of device properties. (g) Estimated (dashed line) and measured (open squares) redox-transistor switching speed scaling with channel area. Reprinted with permission from Ref. [14]. Copyright 2019, American Association for the Advancement of Science.