Numerical and analytical investigations for the SOI LDMOS with alternated high-<italic>k</italic> dielectric and step doped silicon pillars

Numerical and analytical investigations for the SOI LDMOS with alternated high-k dielectric and step doped silicon pillars

Yao Jia-Fei^{1, 2}, Guo Yu-Feng^{1, 2, †}, Zhang Zhen-Yu^{1, 2}, Yang Ke-Meng^{1, 2}, Zhang Mao-Lin^{1, 2}, Xia Tian³

The potential distributions for the HKSD devices (ɛ_D=100, L_d=60μm) and SD devices (L_d=60μm) with different n: (a) n=1, (b) n=2, (c) n=3, (d) n=4.